Magnetic random access memory

What claimed is:




1. A magnetic random access memory which “0” data “1” data are associated with resistance values non-magnetic layer magnetoresistive element, resistance values being variable depending orientation magnetization magnetic free layer magnetic pinned layer which sandwich non-magnetic layer, current let flow first second write current paths, which are provided close magnetoresistive element are separated each other, thereby producing composite write magnetic field, changing direction magnetization free layer, wherein first write current path includes channel region insulated-gate transistor that disposed close free layer, transistor controlled such that channel current with desired magnitude flows transistor.


2. The magnetic random access memory according claim 1, wherein transistor connected write power supply that controlled such that channel current one opposite directions corresponding write data “0” write data “1” caused flow write current.


3. The magnetic random access memory according claim 1, wherein gate wiring continuous with gate electrode transistor provided second write current path, when data written magnetoresistive element, gate wiring supplied with write current one opposite directions accordance with one write data “0” write data “1” transistor controlled such that channel current predetermined direction flows write current that flows first write current path.


4. The magnetic random access memory according claim 1, wherein least part peripheral surfaces gate electrode transistor coated with magnetic material.


5. The magnetic random access memory according claim 1, wherein transistor thin-film transistor.


6. The magnetic random access memory according claim 1, wherein transistor further-functions transistor for read-out cell selection.


7. The magnetic random access memory according claim 6, further comprising first second read-out voltage application terminals, wherein first read-out voltage application terminal connected one end magnetoresistive element, other end magnetoresistive element connected one source drain electrodes transistor via gate electrode transistor, other source drain electrodes connected second read-out voltage application terminal.


8. A magnetic random access memory which “0” data “1” data are associated with resistance values non-magnetic layer magnetoresistive element that includes magnetic free layer magnetic pinned layer which sandwich non-magnetic layer, resistance values being variable depending orientation magnetization magnetic free layer magnetic pinned layer, current let flow least one write current path, which provided close magnetoresistive element, thereby producing write magnetic field, changing direction magnetization free layer magnetoresistive element, wherein write current path includes channel region insulated-gate transistor that disposed close free layer magnetoresistive element, transistor controlled such that channel current, which generates write magnetic field with magnitude corresponding write threshold or more, flows transistor write current.


9. A magnetic random access memory comprising: wiring formed semiconductor substrate; plurality tunneling magnetoresistive elements disposed along wiring intervals, having tunneling magnetoresistive effect that obtained by such structure that non-magnetic layer sandwiched between magnetic pinned layer magnetic free layer; plurality insulated-gate transistors disposed intervals along wiring association with plurality tunneling magnetoresistive elements, each transistors having part wiring gate electrode, channel region that disposed close free layer associated one plurality magnetoresistive elements, wherein transistor controlled such that when data written magnetoresistive element, channel current with desired magnitude flows part write current.


10. The magnetic random access memory according claim 9, wherein free layer pinned layer are set directions spin, which coincide with channel width direction channel region transistor.


11. The magnetic random access memory according claim 10, further comprising: word line formed extend channel width direction channel region gate electrode transistor; bit line formed such that tunneling magnetoresistive element sandwiched between bit line word line, bit line being disposed direction perpendicular word line.


12. The magnetic random access memory according claim 11, wherein time data write, magnetic field that generated by bit current flowing bit line magnetic field that generated by channel current are combined produce write magnetic field, write magnetic field controls direction spin free layer.


13. The magnetic random access memory according claim 12, wherein time data read-out, read-out circuit formed between word line bit line via tunneling magnetoresistive element.


14. The magnetic random access memory according claim 9, further comprising: word line formed extend channel length direction channel region gate electrode transistor; bit line formed such that tunneling magnetoresistive element sandwiched between bit line word line, bit line being disposed direction perpendicular word line.


15. The magnetic random access memory according claim 14, wherein time data write data erasure, magnetic field that generated by bit current flowing bit line magnetic field that generated by channel current are combined produce write magnetic field, write magnetic field controls direction spin free layer.


16. The magnetic random access memory according claim 15, wherein time data read-out, read-out circuit formed between word line bit line via tunneling magnetoresistive element.


17. The magnetic random access memory according claim 9, wherein free layer pinned layer are set directions spin, which coincide with channel length direction channel region transistor.


18. The magnetic random access memory according claim 17, further comprising: word line formed extend channel length direction channel region gate electrode transistor; bit line formed such that tunneling magnetoresistive element sandwiched between bit line word line, bit line being disposed direction perpendicular word line.


19. The magnetic random access memory according claim 18, wherein time data write data erasure, magnetic field that generated by bit current flowing bit line magnetic field that generated by channel current are combined produce write magnetic field, write magnetic field controls direction spin free layer.


20. The magnetic random access memory according claim 18, wherein time data read-out, read-out circuit formed between word line bit line via tunneling magnetoresistive element.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application based upon claims benefit priority prior Japanese Patent Applications No. 2003-065063, filed Mar. 11, 2003; No. 2004-63665, filed Mar. 8, 2004, entire contents both which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field Invention

The present invention relates generally magnetic random access memory (MRAM), more particularly memory cell architecture MRAM that includes magnetic memory cells, each which formed using element that stores “0”/“1” data by tunneling magnetoresistive effect.

2. Description Related Art

In recent years, variety memories, which store data based novel principles, been proposed. Of these, there known MRAM with nonvolatility high operation speed, wherein magnetic memory cells, each which formed using magnetic tunnel junction (MTJ) element that stores “0”/“1” data by tunneling magnetoresistive (TMR) effect, are arranged matrix.

FIG. 14 schematically shows cross-sectional structure MTJ element 70 that used conventional MRAM.

FIGS. 15A 15B illustrate two states directions spin two magnetic layers 71 72 MTJ element 70 shown FIG. 14.

The MTJ element 70 configured such that one non-magnetic layer (tunneling barrier film) 73 interposed between two magnetic layers 71 72 . The MTJ element 70 stores “0”/“1” data, depending whether directions spin two magnetic layers 71 72 are parallel, shown FIG. 15A, or antiparallel, shown FIG. 15B.

Normally, antiferromagnetic layer 74 disposed one two magnetic layers 71 72 . When layer 74 disposed layer 72 , antiferromagnetic layer 74 fixes direction spin magnetic layer 72 . Thus, data easily rewritten by changing only direction spin other magnetic layer 71 . The variable-spin side magnetic layer 71 referred “free layer”, fixed-spin side magnetic layer 72 “fixed layer” (or “pinned layer”).

As shown FIG. 15A, when directions spin (indicated by arrows) two magnetic layers 71 72 are parallel (the same), tunnel resistance tunneling barrier film 73 that sandwiched between two magnetic layers 71 72 decreases minimum (tunneling current increases maximum).

As shown FIG. 15B, when directions spin two magnetic layers 71 72 are antiparallel, tunnel resistance tunneling barrier film 73 that sandwiched between two magnetic layers 71 72 increases maximum (tunneling current decreases minimum).

FIG. 16 schematically shows example plan-view layout memory cell array MRAM that incorporates conventional memory cells. This example illustrates architecture data write mode.

A plurality write word lines WWL plurality bit lines BL are arranged perpendicular each other. At intersections these lines, memory cells each comprising MTJ element are disposed. Each MTJ element rectangular shape with longitudinal axis extending along write word line WWL, with transverse axis extending along bit line BL. The direction spin, which parallel longitudinal axis, given MTJ element. In MRAM, two states with different resistance values MTJ element are associated with “1” data storage state (“1” state) “0” data storage data (“0” state), respectively.

FIG. 17 cross-sectional view, taken along line 15 — 15 FIG. 16, showing example structure of, particular, one memory cell cross section perpendicular write word line WWL.

FIG. 18 cross-sectional view, taken along line 16 — 16 FIG. 16, showing example structure memory cell cross section perpendicular bit line BL.

In FIGS. 17 18, reference numeral 10 denotes semiconductor substrate (e.g. P-type Si substrate); 11 shallow-trench device isolation region (STI); 12 gate oxide film; 13 impurity diffusion layer (N + ) that functions drain region or source region read-out cell select transistor Tr (NMOSFET); 14 gate electrode (GC); 15 first metal wiring layer (M 1 ); 16 second metal wiring layer (M 2 ); 17 MTJ connection wire formed third metal wiring layer (M 3 ); 18 conductive contact for electrically connecting first metal wiring 15 diffusion layer 13 ; 19 conductive contact for electrically connecting second metal wiring layer 16 first metal wiring layer 15 ; 20 conductive contact for electrically connecting third metal wiring layer 17 second metal wiring layer 16 ; 70 MTJ element; 22 fourth wiring layer (M 4 ); 23 conductive contact for electrically connecting fourth metal wiring layer 22 MTJ element 70 ; 24 interlayer insulation film.

In Figures, uses respective wiring layers are defined follows: (BL) bit line for write/read, (WWL) write word line, (SL) source line, (RWL) read-out word line. The source line (SL) connected ground potential.

Now referring FIG. 14 FIG. 18, operational principle data write prior-art MTJ element 70 described.

Data write MTJ performed following manner. As shown FIG. 16, write currents directions, for example, indicated by arrows, are let flow write word line WWL bit line BL. Using composite field magnetic fields Hy Hx generated by these currents, direction spin free layer 71 set parallel or antiparallel, relative pinned layer 72 . Thereby, data written.

For example, when data written MTJ element 70 shown FIG. 16, current first direction or second direction, which opposite first direction, supplied bit line BL accordance with write data, thereby generating magnetic field Hx. A current fixed direction supplied write word line WWL, thereby generating magnetic field Hy. Using composite field produced by magnetic fields Hx Hy, data written. In this case, if current first direction supplied bit line BL, directions spin MTJ element 70 become parallel. If current second direction supplied, directions spin become antiparallel. FIG. 16 illustrates case where direction spin free layer 71 made parallel direction spin pinned layer 72 by composite field.

When data read out MTJ element 70 , read-out word line RWL shown FIGS. 17 18 are activated turn transistor Tr that switching device connected selected MTJ element 70 . Thus, current path formed current let flow selected bit line BL ground potential. As result, current corresponding resistance value selected MTJ element 70 flows only through MTJ element 70 . By detecting current value, data read out.

Referring FIGS. 19 20, how direction spin MTJ element 70 selected by direction applied field described brief.

FIG. 19 shows variation characteristics (MTJ curve) resistance value due reversal applied field MTJ element 70 .

FIG. 20 shows asteroid curve MTJ element 70 .

As indicated by MTJ curve FIG. 19, when magnetic field Hx applied easy-axis direction MTJ element, resistance value (magnetoresistance (MR) ratio) MTJ element 70 changes by, e.g. about 17%. The ordinate FIG. 17 expresses resistance value MTJ element 70 change ratio (i.e. resistance ratio between pre-change post-change). The MR ratio varies depending properties magnetic layers MTJ element 70 . At present, MTJ element with MR ratio about 50% obtained. A composite field easy-axis field Hx hard-axis field Hy applied MTJ element 70 .

As shown by solid lines broken lines FIG. 19, magnitude easy-axis field Hx, which necessary for changing resistance value MTJ element 70 , varies depending magnitude hard-axis field Hy. The broken lines indicate MTJ curves cases where hard-axis field Hy greater than case solid lines. Making use this phenomenon, data written only MTJ element 70 arrayed memory cells, which disposed intersection selected write word line WWL selected bit line BL.

As shown FIG. 20, if magnitude composite field easy-axis field Hx hard-axis field Hy falls outside asteroid curve (e.g. locations indicated by black circular marks), direction spin magnetic layer MTJ element 70 reversed.

On other hand, if magnitude composite field easy-axis field Hx hard-axis field Hy falls inside asteroid curve (e.g. locations indicated by white circular marks), direction spin magnetic layer MTJ element 70 cannot reversed.

Accordingly, data write MTJ element 70 controlled by varying magnitude composite field easy-axis field Hx hard-axis field Hy changing position magnitude composite field Hx-Hy plane.

In above-described prior-art cell architecture shown FIG. 15, however, MTJ element 70 stacked via metal layers that are provided above read-out cell select transistor Tr. This complex stacked structure requires conductor layers interlayer insulation film, including eight metal wiring layers 18 , 15 , 19 , 16 , 20 , 17 , 23 22 one MTJ element 70 . Consequently, great number fabrication steps are needed, it difficult provide MRAM low cost.

BRIEF SUMMARY OF THE INVENTION

According aspect present invention, there provided magnetic random access memory which “0” data “1” data are associated with resistance values non-magnetic layer magnetoresistive element, resistance values being variable depending orientation magnetization magnetic free layer magnetic pinned layer which sandwich non-magnetic layer, current let flow first second write current paths, which are provided close magnetoresistive element are separated each other, thereby producing composite write magnetic field, changing direction magnetization free layer, thus writing data, wherein first write current path includes channel region insulated-gate type transistor that disposed close free layer, transistor controlled such that channel current with desired magnitude flows transistor write current when data written magnetoresistive element.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 cross-sectional view schematically showing example structure memory cell that used MRAM according first embodiment present invention;

FIG. 2 cross-sectional view schematically showing example structure memory cell that used MRAM according second embodiment invention;

FIG. 3 cross-sectional view schematically showing example structure memory cell that used MRAM according third embodiment invention;

FIG. 4 cross-sectional view schematically showing example structure memory cell that used MRAM according fourth embodiment invention;

FIG. 5 cross-sectional view schematically showing example structure memory cell that used MRAM according fifth embodiment invention;

FIG. 6 cross-sectional view schematically showing example structure memory cell that used MRAM according sixth embodiment invention;

FIG. 7 cross-sectional view schematically showing example structure memory cell that used MRAM according seventh embodiment invention;

FIG. 8 perspective view showing memory module according example application MRAM invention;

FIG. 9 cross-sectional view schematically showing example structure memory cell that used MRAM according eighth embodiment invention;

FIG. 10 cross-sectional view schematically showing example structure memory cell that used MRAM according ninth embodiment invention;

FIG. 11 cross-sectional view schematically showing example structure memory cell that used MRAM according tenth embodiment invention;

FIG. 12 cross-sectional view schematically showing example structure memory cell that used-in MRAM according eleventh embodiment invention;

FIG. 13 schematically shows example plan-view layout memory cell array MRAM shown embodiment FIG. 12;

FIG. 14 cross-sectional view schematically showing general architecture MTJ element that used conventional MRAM;

FIG. 15A shows directions spin two magnetic layers MTJ element shown FIG. 14;

FIG. 15B shows directions spin two magnetic layers MTJ element shown FIG. 14;

FIG. 16 schematically shows example plan-view layout memory cell array MRAM that incorporates conventional memory cells;

FIG. 17 cross-sectional view showing example structure of, particular, one memory cell cross section perpendicular write word line shown FIG. 16;

FIG. 18 cross-sectional view showing example structure memory cell cross section perpendicular bit line shown FIG. 16;

FIG. 19 shows variation characteristics resistance value due reversal applied field MTJ element shown FIG. 14;

FIG. 20 shows asteroid curve MTJ element shown FIG. 14.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments present invention now described with reference accompanying drawings.

<First Embodiment>

FIG. 1 cross-sectional view schematically showing example structure memory cell that used MRAM according first embodiment present invention. In descriptions below, structural parts common those shown FIGS. 14 18 are denoted by like reference numerals.

In FIG. 1, reference numeral 10 denotes semiconductor substrate (P-type Si substrate this embodiment); 1 gate oxide film transistor Tr (NMOSFET) that formed semiconductor substrate 10 ; 2 3 drain region source region formed impurity diffusion layers (N + diffusion layers this embodiment), which are selectively formed surface region substrate 10 ; 4 gate electrode; 5 6 drain electrode (contact plug) source electrode (contact plug). The drain source contact plugs 5 6 are formed first wiring layer.

Reference numeral 21 designates MTJ element that provided top gate electrode 4 . Like structure described with reference FIG. 14, MTJ element 21 such structure that non-magnetic layer 73 interposed between free layer 71 pinned layer 72 which are formed magnetic layers. Thus, MTJ element 21 tunneling magnetoresistive effect. An antiferromagnetic layer 74 disposed pinned layer 72 .

The MTJ element 21 this embodiment rectangular shape, each magnetic layers formed magnetic material such NiFe, CoFe, CoCr or CoPt. The direction spin magnetic layers set longitudinal direction rectangular shape MTJ element 21 . In this embodiment, direction spin perpendicular sheet surface FIG. 1. To more specific, longitudinal direction coincides with channel width direction transistor Tr, transverse direction coincides with channel length direction transistor Tr.

Reference numeral 25 denotes first connection wiring (upper wiring this embodiment) that connected pinned layer 72 via antiferromagnetic layer 74 (upper side this embodiment) MTJ element 21 , numeral 26 denotes second connection wiring (lower wiring this embodiment) that connected gate electrode 4 under free layer 71 side (lower side this embodiment) MTJ element 21 .

As described later, time data read-out, read-out voltage Vr applied between upper wiring 25 lower wiring 26 via MTJ element 21 . At time data write, upper wiring 25 or lower wiring 26 functions one current paths for data write. The transistor Tr for data write connected write power supply CS such that when data-is written MTJ element 21 , channel current Ich desired magnitude may flow write current between source drain electrodes 6 5 transistor Tr. A voltage applied predetermined direction transistor Tr according contents data being written.

The material gate electrode 4 not limited, if it does not adversely affect function applying magnetic field, which generated by channel current transistor Tr, free layer 71 MTJ element 21 , described later. The material gate electrode 4 not limited impurity-doped polysilicon which known polysilicon gate. For example, metal silicide layer may provided upper surface polysilicon gate, or metal gate of, e.g. tantalum (Ta), which adopted some types MISFETs, may employed lower wiring 26 .

In this embodiment, gate electrode 4 configured such that metal silicide layer formed upper surface polysilicon gate. That part metal silicide layer, which other than part functioning part gate electrode 4 , used part lower wiring 26 connected MTJ element 21 . For channel on/off control, gate voltage may applied. In this case, such modification may made that gate voltage for controlling on/off state transistor Tr time data write (to described later) applied entire MTJ element 21 , indicated by solid broken lines. In this way, memory cell Mc 1 MRAM formed.

Specifically, memory cell Mc 1 shown FIG. 1 configured such that MTJ element 21 provided top gate electrode 4 transistor Tr, which formed semiconductor substrate 10 . In other words, two write current paths, i.e. lower wiring 26 connected gate electrode 4 channel region transistor Tr, are provided so adjacent free magnetic layer 71 one side MTJ element 21 that formed semiconductor substrate 10 . Alternatively, upper wiring 25 channel transistor Tr may used two write current paths.

A memory cell array formed by arranging plurality memory cells each having structure cell Mc 1 shown FIG. 1 matrix form semiconductor substrate 10 , for example, similar manner shown FIG. 16.

When memory cells each having structure memory cell Mc 1 shown FIG. 1 are arranged form memory cell array, similar manner shown FIG. 16, source drain electrodes 5 6 transistor Tr each MTJ element 21 are connected series write word line WWL shown FIG. 16, for example. Where necessary, gate electrode 4 transistor Tr connected part bit line BL shown FIG. 16.

In addition, Cu wiring, for instance, formed upper wiring 25 so continuous commonly MTJ elements 21 memory cells Mc 1 same row. Further, metal wiring formed word line WWL so continuous series drain electrode 5 source electrode 6 transistor Tr. The transistor Tr functioning write current path device connected metal wiring.

When data write mode, described later, predetermined current made flow through lower wiring 26 . At time data read-out voltage Vr applied between lower wiring 26 upper wiring 25 read-out voltage that produces data read path through MTJ element 21 . The voltage Vr used bit line select voltage for selecting memory cell Mc 1 .

In this way, write word lines WWL bit lines BL are arranged perpendicular each other, MTJ elements 21 are disposed intersections these lines. The MTJ element 21 disposed such that direction spin set width direction gate electrode 4 .

Assuming that memory cell Mc 1 having structure shown FIG. 1 selected the-time data write data read-out. The write read operations memory cell Mc 1 described. In description below, arrows indicate directions current or magnetic field, which are parallel sheet surface Figures. An encircled “X” mark indicates direction current or magnetic field that perpendicular to, extends away from, sheet surface drawing. In addition, encircled dot “●” mark indicates direction current or magnetic field that perpendicular to, extends toward, sheet surface drawing.

When data written selected memory cell Mc 1 , positive write voltage Vgw applied between lower wiring 26 A, which connected gate electrode 4 transistor Tr ground. Specifically, order turn transistor Tr maximum level, gate voltage Vgw that higher than predetermined value applied via wiring 26 A between gate electrode 4 , which corresponds MTJ element 21 , ground potential. Further, indicated by broken line, same voltage Vgw may also applied upper wiring 25 A addition wiring 26 A. As result, magnetic field that generated by current flowing gate electrode 4 applied free layer 71 . At same time, write power supply CS causes channel current Ich (write current), which magnitude enough produce composite magnetic field that greater than write threshold MTJ element 21 combination field generated gate electrode 4 , flow between drain electrode 5 source electrode 6 . In this case, write power supply CS applies potential difference, which polarity corresponding write data “1” or “0”, between drain 5 source 6 . In addition, write power supply CS supplies write current Ich direction “drain 5 →source 6 ” or direction “source 6 →drain 5 ”, accordance with write data “1” or “0”. As result, direction spin free layer 71 set toward, or away from, sheet surface FIG. 1, depending direction composite magnetic field produced by field generated by current flowing gate electrode 4 field produced by channel current Ich.

The direction spin free layer 71 changed by controlling direction field generated by channel current Ich that flows channel transistor Tr. In this case, for example, current perpendicular channel current Ich let flow gate electrode 4 via lower wiring 26 . Thus, it direction channel current Ich that determines direction spin free layer 71 .

As been described above, gate current channel current Ich, which flow directions perpendicular each other, are supplied write currents, resultant magnetic fields produce composite magnetic field. For example, direction magnetization free layer 71 MTJ element 21 changed accordance with direction channel current Ich, thereby writing data. In this case, two directions spin pinned free layers 72 , 71 which are defined longitudinal direction MTJ element 21 along width direction gate electrode 4 (lower wiring 26 , 26 A), are parallel or antiparallel. Data erasure performed same manner data write.

The longitudinal dimension MTJ element 21 may set equal or greater than channel width transistor Tr shown embodiment FIG. 13, for example. The greater width element 21 enhance intensity magnetic field that applied end portions free layer 71 length direction MTJ element 21 .

In embodiment shown FIG. 1, time data read-out, application voltage gate electrode 4 kept low level or zero so turn off transistor Tr.

When data read out read voltage Vr applied between upper wiring 25 lower wiring 26 selected memory cell Mc 1 cross point wiring 25 transistor Tr. The read-out voltage Vr applied between upper wiring 25 , which functions read-out bit line, lower wiring 26 , so that read-out current may flow sense amplifier (not shown) connected upper wiring 25 via MTJ element 21 memory cell Mc 1 . Consequently, read-out current corresponding magnetoresistance value MTJ element 21 flows through MTJ element 21 sense amplifier. Thus, current value detected by sense amplifier that connected read-out bit line or upper wiring 25 , data read out.

According present embodiment, current flowing gate electrode 4 or upper wiring 25 channel current transistor Tr are used write currents. This makes it unnecessary provide fabrication steps forming dedicated metal wiring layers (e.g. write word line WWL FIG. 15) via-contact layers for contact with it, which are required prior art. The number fabrication steps for metal wiring layers reduced.

The gate electrode 4 may formed part lower wiring 26 . Thus, only two metal layers (i.e. first metal layer for drain contact 5 source contact 6 , second wiring layer for upper wiring 25 ) are required. The number fabrication steps for metal wiring layers greatly decreased, manufacturing cost remarkably reduced.

At time data write, current may let flow upper wiring 25 , too. Using composite magnetic field that generated by this current channel current, data write also performed. Thus, value channel current that necessary for write decreased. As result, size transistor Tr reduced, cell size reduced, manufacturing cost further reduced.

<Second Embodiment>

The first embodiment modified such that transistor Tr may also used when data read-out memory cell. An example this architecture described second embodiment invention.

FIG. 2 cross-sectional view schematically showing example structure memory cell Mc 2 that used MRAM according second embodiment invention.

In memory cell Mc 2 , compared memory cell Mc 1 first embodiment, lower wiring 27 , which connected gate electrode 4 provided under MTJ element 21 , electrically connected one end transistor Tr, for example, drain electrode 5 . A tantalum (Ta) film formed gate electrode 4 , for instance, may commonly used connection wiring for lower wiring 27 . The lower wiring 26 A FIG. 1 connected lower wiring 27 . Since structure FIG. 2 same that FIG. 1 other respects, common parts are denoted by like reference numerals.

In operation data write memory cell Mc 2 , high write voltage Vgw that higher than predetermined value applied via lower wiring 26 A, 27 , which gate wiring, between gate electrode 4 ground potential. Thereby, transistor Tr turned on, write power supply CS produces write channel current Ich predetermined direction between drain electrode 5 source electrode 6 transistor Tr, addition current flowing through gate electrode 4 , so produce composite magnetic field.

On other hand, read-out operation, read-out gate voltage Vgr, which lower than write gate voltage Vgw, applied turn transistor Tr. In addition, predetermined read-out voltage Vr applied between upper wiring 25 source electrode 6 , read-out current MTJ element 21 flows, for example, following current path: sense amplifier (not shown)→upper wiring 25 →MTJ element 21 →gate electrode 4 →drain electrode 5 →channel transistor Tr→source electrode 6 →ground.

As been described above, according structure wherein transistor Tr connected series MTJ element 21 , single transistor Tr used commonly write transistor read-out transistor for forming read-out current path via MTJ element 21 .

<Third Embodiment>

FIG. 3 cross-sectional view schematically showing example structure memory cell Mc 3 that used MRAM according third embodiment invention.

The memory cell Mc 3 differs memory cell Mc 1 first embodiment that soft magnetic layer 31 of, e.g. NiFe or CoZrNb coated least part surfaces MTJ element 21 (an upper surface side surfaces this embodiment shown figure). In this case, soft magnetic layer 31 used yoke covers most surfaces MTJ element 21 , except side surfaces free layer 71 . Since structure FIG. 3 same that FIG. 1 other respects, common parts are denoted by like reference numerals.

According this structure, data write operation, larger magnetic field generated by current flowing upper wiring 25 imparted free layer 71 . Accordingly, value channel current Ich (threshold write current) transistor Tr, which required for data write, decreased. As result, for example, channel width write transistor Tr reduced, cell size reduced, manufacturing cost further reduced. Although not shown, this third embodiment, too, write power supply connected embodiments FIGS. 1 2. In embodiments FIGS. 4 7 that are described below, write power supply, though not shown, similarly connected.

<Fourth Embodiment

In first third embodiments, direction magnetization free layer 71 MTJ element 21 perpendicular direction channel current (i.e. gate width direction gate electrode 4 ). However, direction magnetization free layer 71 MTJ element 21 may set parallel direction channel current (i.e. channel length direction). An embodiment described below.

FIG. 4 cross-sectional view schematically showing structure memory cell Mc 4 that used MRAM according fourth embodiment invention.

The memory cell Mc 4 differs memory cell Mc 3 that MTJ element 21 disposed such that directions magnetization free layer 71 pinned layer 72 coincide with channel length direction transistor Tr. Since structure FIG. 4 same that FIG. 3 other respects, common parts are denoted by like reference numerals.

With above structure, when data written, channel current Ich, which parallel sheet surface FIG. 4, caused flow transistor Tr selected memory cell Mc 4 . In addition, current with predetermined magnitude form composite magnetic field with channel current Ich exceeding write threshold MTJ element 21 caused flow upper wiring 25 including antiferromagnetic layer 74 direction perpendicular sheet surface FIG. 4 accordance with write data “1” or “0”. Thereby, direction magnetization or spin free layer 71 MTJ element 21 switched. Thus, current Ich that flows channel transistor Tr fixed one direction, shown FIG. 4.

<Fifth Embodiment>

FIG. 5 cross-sectional view schematically showing structure memory cell Mc 5 that used MRAM according fifth embodiment invention.

The memory cell Mc 5 differs memory cell Mc 1 first embodiment following respects. The semiconductor substrate formed as, e.g. SOI (silicon insulator). Specifically, semiconductor substrate semiconductor layer 50 formed SOI substrate 100 made insulator such glass. A thin-film transistor Trth formed semiconductor substrate 50 transistor for providing channel current Ich. In other respects, structure FIG. 5 same that FIG. 1, common parts are denoted by like reference numerals.

According fifth embodiment, array thin-film transistors Trth stacked on, e.g. underlying logic circuit section that formed semiconductor substrate. Therefore, so-called system-on-silicon structure easily formed low cost.

<Sixth Embodiment>

FIG. 6 cross-sectional view schematically showing structure memory cell Mc 6 provided MRAM according sixth embodiment present invention.

The memory cell Mc 6 differs memory cell Mc 5 fifth embodiment that soft magnetic film 61 made NiFe or CoZrNb disposed under thin-film transistor Trth. The soft magnetic film 61 buried under entire surface SOI substrate 100 . In other respects, structure FIG. 6 same that FIG. 5, so common parts are denoted by like reference numerals.

According this structure, soft magnetic film 61 disposed such that region semiconductor substrate 50 where channel region transistor Trth formed sandwiched between soft magnetic layer 61 MTJ element 21 . Thus, composite magnetic field generated by channel current Ich well current flowing gate electrode 4 or layer 74 acting free layer 71 write operation, for example, greatly enhanced. As result, magnitude channel current Ich remarkably decreased, size, e.g. channel width, transistor Trth further reduced.

<Seventh Embodiment>

FIG. 7 cross-sectional view schematically showing structure memory cell Mc 7 that used MRAM according seventh embodiment present invention.

The memory cell Mc 7 differs memory cell Mc 1 first embodiment shown FIG. 1 following respects:

(1) Like embodiment shown FIG. 3, yoke soft magnetic film 31 made of, e.g. NiFe or CoZrNb coated least part surfaces MTJ element 21 (an upper surface side surfaces this embodiment);

(2) A thin-film transistor Trth formed semiconductor layer 50 write current supply transistor;

(3) A soft magnetic film 61 made of, e.g. NiFe or CoZrNb, disposed SOI substrate 100 under thin-film transistor Trth;

(4) Wiring 27 that connected free layer 71 MTJ element 21 provided separately gate electrode 4 , wiring 27 that connected free layer 71 MTJ element 21 electrically connected one end transistor Trth, e.g. drain electrode 5 .

In other respects, structure FIG. 7 same that FIG. 1, so common parts are denoted by like reference numerals. A magnetic film for forming free layer 71 may extended drain electrode 5 connection wiring 27 .

When data written memory cell Mc 7 with above structure, current with sufficient magnitude exceeding write threshold MTJ element 21 together with current flowing layer 74 , for example, required flow channel current Ich transistor Trth, like first embodiment. Hence, it necessary set transistor Trth full turn-on state, gate voltage set value that necessary for fully driving transistor Trth.

At time read-out, potential gate electrode 4 set on-state which read-out current, which less than write current for MTJ element 21 by order magnitude or more, flows channel current transistor Trth. Although not shown FIG. 7, read-out path same embodiment FIG. 2. At times other than write/read/erasure modes, gate voltage gate electrode 4 set off-state which no channel current Ich flows transistor Trth.

Since selected MTJ element 21 separated other memory cells not only write time but also read-out time, read-out speed increased.

<Modification>

FIG. 8 perspective view showing memory module according example application MRAM according each embodiment invention.

The memory module includes memory chip 81 that configured such that given number memory cell arrays configured according one embodiments present invention are stacked semiconductor substrate order increase memory capacity. The memory chip 81 stacked driver chip 82 wherein driver circuits for cell section are formed semiconductor substrate. A logic chip wherein logic circuits formed semiconductor substrate for write/read control memory chip 81 may also substituted for driver chip 82 . The stacked structure packaged memory module shown FIG. 8.

According this memory module, structures chips 81 82 are simplified. Thus, manufacturing yield each chip 81 , 82 yield entire module are improved, manufacturing cost further reduced.

Next, referring FIGS. 9 11, basic architectures operations memory cells according still further embodiments present invention now described detail. In FIGS. 9 11, structural components common those FIGS. 1 7 are denoted by like reference numerals symbols.

<Eighth Embodiment>

In FIG. 9, word line 4 w that extends channel width direction provided channel region transistor Tr via gate insulation film 1 . A free layer 71 MTJ element 21 provided contact with upper surface word line 4 w . A bit line 25 b , which extends direction perpendicular word line 4 w , provided contact with upper surface antiferromagnetic layer 74 that formed pinned layer 72 MTJ element 21 . The direction spin pinned layer 72 set perpendicular to, extends toward, sheet surface FIG. 9. The word line 4 w disposed along direction spin free layer 71 pinned layer 72 .

At time manufacture, drain contact 5 source contact 6 are formed first metal wiring contact with surfaces drain region 2 source region 3 formed semiconductor substrate 10 . Subsequently, 4-layer MTJ element 21 formed word line 4 w . After entire surface substrate 10 covered with interlayer insulation film (not shown), antiferromagnetic layer 74 exposed bit line 25 b formed. Thus, basic structural part memory cell McB this embodiment formed.

In embodiment shown FIG. 9, direction spin pinned layer 72 perpendicular to, extends toward, sheet surface FIG. 9. Assume that direction spin free layer 71 opposite that pinned layer 72 perpendicular to, extends away from, sheet surface FIG. 9.

In state which predetermined potential difference provided by write power supply CS between drain region 2 source region 3 , “HIGH” gate voltage applied word line 4 w that selected by address decoder (not shown). As result, channel current Ich flows transistor Tr, for example, direction arrow FIG. 9. By channel current Ich, magnetic field direction toward sheet surface FIG. 9 applied free layer 71 .

On other hand, bit line current Ib flows bit line 25 b , which selected by address decoder (not shown), direction arrow FIG. 9. A magnetic field that generated by bit line current Ib applied free layer 71 direction toward sheet surface FIG. 9. As result, composite field two magnetic fields applied free layer 71 , direction spin free layer 71 reversed become direction toward sheet surface FIG. 9. Thus, data written memory cell Mc 8 .

At time read-out, voltage word line 4 w decreased “LOW” level, transistor Tr set off-state. If cell Mc 8 selected this state, voltage applied between bit line 25 b word line 4 w . At this time, directions spin pinned layer 72 free layer 71 are parallel, resistance value MTJ element 2 low. A read-out current flows through MTJ element 21 . The read-out current fed sense amplifier (not shown) via bit line 25 b , data read out cell Mc 8 . On other hand, when directions spin pinned layer 72 free layer 71 are antiparallel, resistance MTJ element 21 high read-out current low. Thus, data corresponding this state read by sense amplifier.

<Ninth Embodiment>

Next, referring FIG. 10, structure operation memory cell Mc 9 according another embodiment invention described. In embodiment FIG. 10, word line 4 w extends channel length direction transistor Tr. A drain contact 5 source contact 6 are formed drain region 2 source region 3 such positions that drain contact 5 source contact 6 are not contact with word line 4 w . On other hand, bit line 25 b formed extend width direction transistor channel that perpendicular bit line 25 b . The MTJ element 21 sandwiched between word line 4 w bit line 25 b intersection word line 4 w bit line 25 b such that MTJ element 21 corresponds position channel region transistor Tr. In this case, directions spin pinned layer 72 free layer 71 are perpendicular sheet surface FIG. 10, like case-shown FIG. 9.

The embodiment shown FIG. 10 configured such that connection drain region 2 source region 3 reversed relation polarity write power supply CS. Thus, relationship potential between source drain reversed, channel current Ich selectively set so flow opposite directions accordance with polarity connection power supply CS. On other hand, direction bit line Ib that flows bit line 25 b fixed one direction away form sheet surface FIG. 10, shown FIG. 10. Like embodiment shown FIG. 9, wiring layers are drain contact 5 , source contact 6 , word line 4 w , bit line 25 b which, along with word line 4 w , sandwiches MTJ element 21 . Thus, architecture fabrication process are simple.

When data written memory cell Mc 9 FIG. 10, direction spin free layer 71 set previously direction away sheet surface FIG. 10, which opposite direction spin pinned layer 72 case FIG. 9 embodiment. When gate voltage applied word line 4 w this state, transistor Tr turned channel current Ich flows source region 3 drain region 2 . By channel current Ich, magnetic field direction away from-the sheet surface FIG. 10 generated. At this time, if bit current Ib direction arrow flows bit line 25 b , bit current Ib produces magnetic field perpendicular direction spin free layer 71 . These orthogonal magnetic fields are combined produce composite field. If component composite field, which toward direction opposite previously set direction spin free layer 71 , exceeds predetermined intensity, direction spin reversed become direction toward sheet surface FIG. 10. As result, predetermined data written. In this case, magnitude bit current Ib may equal that current Iw that flows word line 4 w.

When data erased, polarity power supply CS, which applies voltage between drain region 2 source region 3 , reversed, while bit current Ib maintained same direction write time. As result, channel current Ich reversed, generated magnetic field changed direction away sheet surface FIG. 10. Consequently, direction composite field becomes opposite direction for data write, direction spin free layer 71 reversed become direction away sheet surface FIG. 10. Thus, data erased.

At time data read-out, state which transistor Tr off-state, read-out current flows between bit line 25 b word line 4 w , which are selected by address decoders (not shown). A sense amplifier (not shown) connected bit line 25 b senses magnitude current flowing MTJ element 21 , thus reading out data.

<Tenth Embodiment>

FIG. 11 shows memory cell Mc 10 according still another embodiment invention. In this embodiment, unlike embodiment shown FIG. 10, direction channel current Ich fixed one direction source region 3 toward drain region 2 . Instead, direction bit current Ib flowing bit line 25 b made selectable between two opposite directions. In addition, directions spin free layer 71 pinned layer 72 MTJ element 21 are set agree with channel length direction.

Assume that initial state direction spin free layer 71 direction indicated by broken-line arrow FIG. 11. At time data write, “HIGH” voltage applied word line 4 w that gate electrode selected by address decoder (not shown), thereby turning transistor Tr. As result, channel current Ich flows direction indicated by arrow FIG. 11, magnetic field perpendicular direction spins MTJ element 21 generated.

On other hand, if current flows bit line 25 b , which selected by address decoder (not shown), direction toward sheet surface FIG. 11, this current produces magnetic field direction opposite initial direction spin free layer 71 that indicated by solid-line arrow. As result, composite field produced by magnetic field generated by current flowing bit line 25 b magnetic field generated by channel current Ich. If composite field magnitude exceeding predetermined value, direction spin free layer 71 changes direction broken-line arrow direction solid-line arrow. Thereby, data written.

In case data erasure, state which transistor Tr turned channel current Ich flows direction indicated by arrow, bit current Ib caused flow bit line 25 b direction away sheet surface FIG. 11. As result, composite field direction opposite direction for data write generated, direction spin free layer 71 reversed become direction indicated by broken-line arrow. This referred direction erasure.

At time read-out, voltage word line 4 w that gate electrode lowered turn off transistor Tr. In this state, MTJ element 21 , which sandwiched between word line 4 w bit line 25 b that are selected by address decoders, selected. The sense amplifier (not shown) connected bit line 25 b detects magnitude bit current that varies depending resistance value MTJ element 21 , which determined according whether direction spin free layer 71 same direction spin pinned layer 72 . Thus, data read out.

<Eleventh Embodiment>

Data write may also performed by merely using magnetic field generated by channel current flowing through transistor Tr instead composite magnetic field embodiments FIGS. 1 11.

In FIGS. 12 13, plurality lower wirings 26 B 1 , 26 B 2 each connected gate electrode 4 transistors Tr are arranged one direction. Upper wirings 25 c 1 , 25 c 2 are arranged above lower wirings 26 B 1 , 26 B 2 via MTJ elements 21 . A pair source line 28 drain line 29 are arranged direction crossing wirings 26 B 1 , 26 B 2 . Source contact 6 each transistor Tr connected source line 28 drain contact connected drain line 29 .

Referring FIGS. 12 13, memory cell Mc 11 selected by selecting lower wiring 26 B 1 connected gate electrode 4 bit line direction. In word line direction, source line 28 connected source contact 6 transistor Tr selected turn-on voltage Von applied between source line 28 ground line 29 connected drain contact 5 transistor Tr.

In data write operation, gate voltage Vgw applied gate electrode 4 write current applied between source contact 6 drain contact 5 via source line 28 drain line 29 connected ground. Thus, selected memory cell Mc 11 , transistor Tr turned flow channel current Ich write power supply (not shown).

In this case, no magnetic field generated gate electrode 4 . A magnetic field enough determine direction spin free layer 71 generated channel current Ich flowing through transistor Tr.

When polarity write power supply changed reverse direction with respect transistor Tr, polarity voltage Von applied between source drain lines 28 29 may reversed so that channel current Ich reversed reverse spin direction free layer 71 , thereby determining contents data being written MTJ element 21 .

In data read operation, read voltage Vr applied between upper wiring 25 c 1 wiring 26 B 1 connected free layer 71 MTJ element 21 shown FIG. 12. The remaining structure FIGS. 12 13 similar that shown FIG. 1.

The present invention applicable case where free layer MTJ element each embodiment multi-layer structure lieu single-layer structure. For example, free layer 71 may made first free layer 71 made first magnetic material second free layer 71 b made second magnetic material shown FIG. 1.

As been described above, magnetic random access memory according present invention realize very simple cell structure, while manufacturing cost greatly reduced.

Additional advantages modifications readily occur those skilled art. Therefore, invention its broader aspects not limited specific details representative embodiments shown described herein. Accordingly, various modifications may made without departing spirit or scope general inventive concept defined by appended claims their equivalents.