Magnetic memory device structure

What claimed is:




1. A magnetic processing circuit comprising: magnetic element having variable magnetization state which set response one or more input signals; wherein magnetic element shape that includes curved portion asymmetric along least first axis.


2. The magnetic processing circuit claim 1, wherein said magnetic element part memory cell, said variable magnetization state corresponds date value stored said memory cell.


3. The magnetic processing circuit claim 1, wherein said magnetic element part logic gate, said variable magnetization state corresponds logic function performed said one or more input signals.


4. The magnetic processing circuit claim 1, wherein said shape symmetric along second axis which perpendicular said first axis.


5. The magnetic processing circuit claim 1 wherein said shape includes both concave portion convex portion.


6. The magnetic processing circuit claim 1 wherein said magnetic element situated over silicon substrate.


7. The magnetic processing circuit claim 1, wherein said magnetic element part magnetic field sensor.


8. A magnetic processing circuit comprising: magnetic element having variable magnetization state which set response one or more input signals; wherein magnetic element shape that symmetric along first axis asymmetric along second axis which perpendicular said first axis.


9. The magnetic processing circuit claim 8, wherein said magnetic element part memory cell, said variable magnetization state corresponds date value stored said memory cell.


10. The magnetic processing circuit claim 8, wherein said magnetic element part logic gate, said variable magnetization state corresponds logic function performed said one or more input signals.


11. The magnetic processing circuit claim 8, wherein said shape includes least one curved portion.


12. The magnetic processing circuit claim 8 wherein said shape includes both concave portion convex portion.


13. The magnetic processing circuit claim 8 wherein said magnetic element situated over silicon substrate.


14. The magnetic processing circuit claim 8, wherein said magnetic element part magnetic field sensor.


15. A magnetic memory cell comprising: magnetic element which stores data for memory cell form variable magnetization state; wherein magnetic element shape that symmetric along first axis asymmetric along second axis which perpendicular said first axis.


16. The magnetic memory cell claim 15, wherein said magnetic element includes cobalt, iron, permalloy, iron-cobalt, and/or Heusler alloy.


17. The magnetic memory cell claim 15, wherein said magnetic element situated silicon substrate.


18. The magnetic memory cell claim 15, wherein said second axis easy magnetization axis.


19. The magnetic memory cell claim 15, wherein said shape includes least one curved portion.


20. The magnetic memory cell claim 19, wherein said shape includes both concave portion convex portion.


21. The magnetic memory cell claim 19, wherein said shape also includes straight portion.


22. The magnetic memory cell claim 19, wherein said curved portion aligned along said second axis.


23. The magnetic memory cell claim 19, wherein said magnetic element shape first convex portion, further including second magnetic element situated opposite said magnetic element, which second magnetic element convex shape portion which faces said first convex portion.


24. The magnetic memory cell claim 23, wherein said magnetic element said second magnetic element different coercivities.


25. An electron spin based memory cell comprising: ferromagnetic layer which imparts variable impedance spin polarized current conducted electron spin based memory cell; wherein ferromagnetic layer shape that symmetric along first axis asymmetric along second axis which perpendicular said first axis; wherein said spin polarized current read determine data value stored electron spin based memory cell.


26. The electron spin based memory cell claim 25, wherein said ferromagnetic layer includes cobalt, iron, permalloy, iron-cobalt, and/or Heusler alloy.


27. The electron spin based memory cell claim 25, wherein said ferromagnetic layer includes ferromagnetic metal, semiconductor, perovskite, and/or semimetal.


28. The electron spin based memory cell claim 25, wherein said magnetic element situated silicon substrate.


29. The electron spin based memory cell claim 25, wherein said second axis easy magnetization axis.


30. The electron spin based memory cell claim 25, wherein said shape includes least one curved portion.


31. The magnetic memory cell claim 30, wherein said shape includes both concave portion convex portion.


32. The magnetic memory cell claim 30, wherein said shape also includes straight portion.


33. The magnetic memory cell claim 30, wherein said curved portion aligned along said second axis.


34. The magnetic memory cell claim 30, wherein said magnetic element shape first convex portion, further including second magnetic element situated opposite said magnetic element, which second magnetic element convex shape portion which faces said first convex portion.


35. The magnetic memory cell claim 34, wherein said magnetic element said second magnetic element different coercivities.

FIELD OF THE INVENTION

This invention relates generally hybrid electronic devices comprised semiconductor structures combination with ferromagnetic components. In particular, present invention directed spin polarized electron conduction device formed ferromagnetic films. The ferromagnetic components contribute new parameters devices permitting new applications improved performance environments such non-volatile memory storage.

BACKGROUND OF THE INVENTION

The semiconductor Field Effect Transistor (FET), fabricated typically metal oxide semiconductor (MOSFET) structure silicon substrate or Gallium Arsenide (GaAsFET) device Gallium Arsenide substrate, building block modern digital electronics. For example, memory cells for storage binary information logic gates for processing digital data streams both use FETs primary components.

A review cell structures various prior art memory devices follows. Some these, such leading volatile memory technology (i.e. memory which lost when power not applied, such dynamic random access memory (DRAM)) use conventional semiconductor FET structures capacitors their cell designs. A number alternative memory technologies that are nonvolatile (i.e. memory retained when power not applied) use magnetostatic coupling magnetoresistors comprised ferromagnetic elements effectuate data storage function. In addition, recent non-volatile device proposed by present applicant (see U.S. Pat. No. 5,432,373) using magnetic spin transistor with one or more passive elements also reviewed.

Finally, brief review operation typical logic gates based conventional FET technology also provided.

Cell Structures Used Conventional Volatile Memory Devices

In case memory cells used DRAMs, most common commercial cell consists only two elements, capacitor for data storage field effect transistor (FET) for isolation array. This cell popular because cell size made small, resulting high packing density relatively low production cost. The storage element capacitor, two stable states representing binary data “1” or “0” be, for example, states with stored charge Q or with stored charge 0 . Every cell connected array write read wires, also called “bit” “word” lines. Since one capacitor linked together with other capacitors array lose its charge its neighbor, capacitor each cell connected transistor within that cell so isolated array. When transistor “on” there low resistance write or read wire so that applied voltage charge capacitor during write process or sense circuit determine stored charge during read process. When transistor “off,” high impedance write or read wire isolates capacitor electrically any other element array.

Typically, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for use DRAM fabricated by standard lithographic processing techniques silicon substrate. The oxide that isolates gate channel highly insulating, so that metallized gate capacitance rest device. In some designs gate capacitance used storage capacitance. Reading performed with sense circuit that compares charge (or voltage) C with charge (or voltage) standard capacitor C′ dummy cell. Readout voltages are order 10 100 mV stored charge Q order million electrons.

The conventional DRAM memory device, however, suffers number operational physical drawbacks. For one, memory volatile. Unavoidable leakage currents discharge capacitor so that each cell must refreshed constantly, i.e. read rewritten, approximately every few milliseconds. Furthermore, background alpha-particle radiation induce sufficient conductance MOSFET drain capacitor spuriously, erasing memory that cell.

Finally, cell dimensions are not shrinking limit permitted by lithography because restrictions capacitor FET size. Consequently, there are limits how dense these devices made using conventional techniques.

Cell Structures Used Alternative Non-Volatile Memory Devices

Several alternative technologies used make nonvolatile memory cells. Capacitive memory elements utilizing ferroelectric material dielectric undergone decades development work, but still suffer fatigue: they cannot provide infinite number read/write cycles.

Several competing approaches use ferromagnetic materials. Three such technologies are reviewed below.

Magnetoresistive Random Access Memory (MRAM)

Magnetoresistive Random Access Memory was proposed decade ago [J. M. Daughton, “Magnetoresistive Memory Technology,” Thin Solid Films 216, 162 (1992)] This device employs array bit word lines. Each bit line divided into n storage cells. Each cell trilayer composed ferromagnetic metal base layer, nonmagnetic metal middle layer, ferromagnetic metal top layer. Note that F-N-F geometry not same giant magnetoresistance (GMR) structures; layers are so thick that interfacial spin scattering F-N interfaces negligible fraction all scattering events, there no exchange coupling across N layer. The cell length l, width w thickness d. Looking cell cross section across width, there are two stable magnetization states determined by magnetostatic coupling, each with magnetization two ferromagnetic films oriented opposing directions: clockwise counterclockwise.

The resistance each cell, measured with sense current applied along length cell, function anisotropic magnetoresistance (AMR) F layers. It value R 1 when magnetizations are perpendicular sense current (as case for either stable magnetization state) R 1 ′ if magnetizations ferromagnetic layers are forced lie parallel sense current. Each cell bit line connected next cell with conducting strip which resistance R c .

Columns n word lines cross m rows bit lines. Each nonmagnetic word line crosses top cell each bit line. The state cell (i,j) written by sending current pulses appropriate amplitude through bit line i word line j, using magnetic fields currents cause magnetization cell orient either clockwise or counterclockwise. The contents cell are read by first biasing word line j with large enough current so that fields current cause magnetizations both ferromagnetic layers canted orientation that approximately 45 degrees away axis bit line.

In this orientation resistance cell (for sense current applied along bit line) value R 2 that between R 1 R 1 ′. Next, sense current applied along bit line, voltage measured across bit line, having value proportional (n−1)R 1 +R 2 +nR c . Finally, read current pulse applied word line, addition original bias current. The field this current pulse changes magnetization orientation direction more nearly parallel sense current if initial orientation was clockwise, or direction more nearly perpendicular sense current if initial orientation was counterclockwise. Thus, voltage across bit line either increases or decreases when read pulse applied. A sense circuit that measures changes voltage records positive or negative change “1” or “0.”

By using derivative sense technique, MRAM avoids necessity electrically isolating each cell. However, this approach for non-volatile memory element also suffers number drawbacks.

To begin with, readout voltage quite small signal noise ratio poor. The change resistance that must sensed during read process small fraction R 1 , this small change must distinguished background approximately nR 1 +R c . In practice, two elements are fabricated for each cell, thus doubling signal, read process repeated several times so that final readout taken average repeated samplings, thus lowering noise. This increases time for read cycle. Power dissipation relatively large during readout because relatively large currents must applied long, resistive lines. Finally, errors introduced during readout if bias current tips magnetization into unstable state.

MRAM with GMR Elements

Another conventional approach uses magnetoresistor R storage element, cell comprised R, reference resistor R′, two or three FETs isolate cell rest array. The magnetoresistor R typically thin film ferromagnetic metal (or ferromagnetic/nonmagnetic metal multilayer) resistor with length l, width w thickness d, two values, R′ R′+δR, corresponding two stable magnetization states.

For example, one state magnetization permalloy film might parallel direction flow sense current, I sense , other state magnetization might perpendicular I scene . For GMR elements, one state corresponds magnetizations ^M 1 ^M 2 F 1 F 2 aligned parallel (or magnetizations M i all ferromagnetic layers multilayer stack aligned parallel), other state ^M 1 ^M 2 are antiparallel (or alternate ferromagnetic layers multilayer stack are antiparallel). The magnetization state written by using magnetic field generated by current pulses applied array write lines.

The read process begins by selecting cell. When cell addressed isolating FETs are set “on” state by driving appropriate word line high voltage. In this state FETs conduct current with some low resistance, order 1000 Ω or less. A bias current I sense then applied both magnetoresistor R reference resistor R′. A sense circuit end line cells compares two voltages interprets “1” or “0” when, for example, I Sense *(R−R′)>0 or I sense *(R−R′)=0 respectively. The voltage levels corresponding “1” (or “0”) are then amplified TTL or CMOS levels.

The voltage I sense *δR that distinguishes “1” “0” must large enough for reliable discrimination. Since magnetoresistive ratio δR/R′ ferromagnetic films (or GMR multilayers) small, 10 percent or less, magnetoresistor must made quite large. For example, with R=100 Ω δR/R′=0.06, reasonable bias current 1 mA would produce readout voltage difference only 6 mV, poor signal noise ratio characteristic GMR cells.

This approach several other drawbacks. A resistor occupies substantial area cell. Continuing above example, 100 Ω magnetoresistor could fabricated using ferromagnetic materials with resistivities about 20 μΩ-cm, with length l=5 μm, width w=1 μm, thickness d=0.01 μm. In addition, this cell requires fabrication two resistors, R R′, thus requiring additional isolation FETs and, all together, taking up considerable space. The reference resistor cannot placed outside cell because resistive difference, δR, so small that resistance each memory resistor must matched particular reference. Since resistance function temperature, R=R(T), reference resistor must fabricated very near magnetoresistor so that both resistors always same temperature, material for reference resistor must carefully chosen so that temperature dependence its resistivity similar that magnetoresistor. Finally, resistance each cell quite large. When numerous cells are placed single read line, array, resistance read line substantial. Since read process uses current bias, power dissipated each read cycle relatively large.

Spin Transistor Nonvolatile RAM (NRAM)

Active devices using magnetic spin transport are well known art. The history spin transport begins with experiment by Meservey [R. Meservey, P. M. Tedrow P. Fulde, Phys. Rev. Lett. 25, 1270 (1970); P. M. Tedrow R. Meservey, Phys. Rev. Lett. 26, 192 (1971); Phys. Rev. B 7, 318 (1973)] where it was shown that electric current tunneling ferromagnetic electrode across low transmission barrier into superconducting detector carried net spin polarization. A later spin injection experiment [described several journals, including Mark Johnson R. H. Silsbee, Phys. Rev. Lett. 55, 1790 (1985); Phys. Rev. B 35, 4959 (1987); Phys. Rev. B 37, 5312 (1988); Phys. Rev. B 35, 5326 (1988)] then demonstrated that (i) current driven across any ferromagnet-nonferromagnet (F 1 -N) interface carried net spin polarization, (ii) that nonequilibrium population spin polarized electrons, equivalently nonequilibrium magnetization ˜M, diffused away F 1 -N interface into N with characteristic length equal classic spin diffusion length δ s , (iii) that nonequilibrium magnetization N affected current flow (or voltage developed) N-F 2 interface second ferromagnetic film.

The idea incorporating spin injection effects semiconductors was mentioned art even before spin injection experiment by present applicant proved validity phenomenon. Indeed, Aronov [A. G. Aronov, Sov. Phys. JETP 24, L32 (1976)] proposed that current driven ferromagnet into semiconductor would spin polarized, that spin polarization current semiconductor (N) would maintained over length scale diffusion length. However, date applicant unaware any known successful implementations these proposals.

Datta Das, citing spin injection experiment performed by applicant, noting long spin diffusion lengths measured aluminum (δ s approximately 0.5 mm low temperature), proposed [S. Datta B. Das, Appl. Phys. Lett. 56, 665 (1990)] device illustrated FIG. 2 wherein spin injection extended FET-like structure: iron contacts are employed source drain gate voltage was used modulate source-drain current allowing device perform current modulator. According their proposed device nonmagnetic metal gate 174 fabricated Schottky (or insulating) barrier 176 top layer InAlAs 178 that grown InGaAs substrate 180 . The InAlAs—InGaAs interface forms high conductance Two Dimensional Electron Gas (2DEG) 182 region that acts conducting channel between source drain, which are thin iron films 170 fabricated either side gate 174 contact with 2DEG 182 . The magnetizations, ^M s 184 ^M d 186 , source drain ferromagnetic films are always aligned parallel along ^x direction. The source provides spin polarized electrons channel with spin axes electrons oriented parallel magnetization source drain, along ^x. Because spin injection effect source—drain conductance proportional projection spin orientation polarized electrons reaching drain orientation drain magnetization. A voltage V g 172 applied gate 174 generates electric field along ^z along with associated effective magnetic field along ^y, causes spin axis each electron precess [refer description Rashba effect above article by Datta Das]. Thus, orientation spin axes current carrying electrons relative magnetization 186 drain function gate voltage 172 : source-drain conductance (and current) modulated periodically gate voltage monotonically increased, device proposed by Datta Das functions current modulator.

The Datta Das device, however, not yet been sucessessfully fabricated demonstrated, concept never been adapted used conventional FET because Schottky barrier semiconductor—iron interface damages device performance by introducing large resistances source drain. It also likely (though unproven) that Schottky barrier acts impede flow spin polarized electrons by randomizing spin orientation each electron. Neither Datta Das device concept been adapted used memory element because magnetizations ^M s ^M d were locked parallel configuration. Furthermore, polarized spins were injected with orientation along ^x so that they would precess under influence effective magnetic field (associated with gate voltage) along ^y, length 2DEG conducting channel was designed sufficiently long that spin polarized electrons could accumulate large phase angles result their precession. In practice, precession under influence field along ^y leads randomization spin orientation acts destroy knowledge initial state spin polarized electron; therefore information memory state (of source or drain) lost.

A replacement for conventional semiconductor devices was proposed by present applicant connection with device known bipolar spin transistor. This device related modifications described-in Mark Johnson, “The All Metal Spin Transistor,” I.E.E.E. Spectrum Magazine, Vol. 31 No. 5 p. 47 (1994); Mark Johnson, “The Bipolar Spin Transistor,” Science 260, 320 (1993). This device depicted FIG. 1, with F 1 150 F 2 152 arranged one side bulk sample aluminum 154 . F 1 150 injects source diffusing spin polarized electrons 156 F 2 152 detects their presence. This device novel F-N-F structure that used circuit element nonvolatile memory cell several advantages. Since readout voltage bipolar, positive for ^M 1 ^M 2 parallel negative for ^M 1 ^M 2 antiparallel, discrimination between logical “1” “0” relatively easy; each cell needs only single storage element whose readout compared with ground. Furthermore, transimpedance spin transistor scales inversely with size, so readout voltage larger (for constant current) for smaller devices, thus promoting shrinking cell size.

Two characteristics device must taken into consideration when using device NRAM. First, device fabricated entirely metals, therefore characterized by low electrical impedance. Thus, fabricate array such elements it necessary electrically isolate each element others array, so that output any element not shorted ground through neighboring element. Second, output voltages available device are less than TTL or CMOS levels, output must therefore amplified before it incorporated TTL or CMOS circuits.

Another spin transistor NRAM cell design [Mark Johnson, “Magnetic Spin Transistor,” U.S. Pat. No. 5,432,373, issued Jul. 11, 1995] composed spin transistor one or more capacitors resistors. The passive elements provide isolation for spin transistor each cell, readout voltage was transmitted end line elements for amplification. A drawback this design that resistors capacitors take up substantial space chip. Thus, substantial portion (even majority) cell area occupied by passive elements, packing densities are limited, unique scaling feature spin transistor wasted.

Furthermore, cell isolation not very efficient readout voltage degraded during transmission sense circuit, resulting higher noise lower readout sensitivity. More recent proposals for spin transistor memory cell designs [see applications referenced above] incorporate spin transistor with one (or more) isolating FETs. This practical approach, achieve packing densities comparable with, or higher than, DRAM.

However, until present invention it been impossible integrate functions nonvolatile storage cell isolation single element.

FET Logic Gates

Logic operations computing devices are typically performed with digital voltage pulses FET gates that are linked together appropriate way. To provide example that permits brief critical discussion, standard arrangement [Paul Horowitz Winfield Hill, “The Art Electronics,” Cambridge Univ. Press, Cambridge U.K. (1980); see p. 328] for AND gate operation depicted FIG. 3 where each element Q i enhancement mode FET. Q 1 10 , Q 2 12 Q 5 18 are p-channel FETs. A p-channel FET high impedance, therefore “off” state, when gate voltage zero or positive. It low impedance, therefore “on” state, when gate voltage lower than threshold value below zero (where threshold value typically 0.5 Volt or less). Q 3 14 , Q 4 16 Q 6 20 are n-channel FETs. An n-channel FET “off” when gate voltage below ground “on” when gate voltage larger than threshold value above ground. Voltage pulses positive or zero amplitude (HIGH or “1”; or LOW or “0”) are applied simultaneously inputs A 22 B 24 , cell operates AND gate following way.

When inputs A 22 B 24 are HIGH (“1”+“1”), Q 3 14 Q 4 16 are “on”, Q 1 10 Q 2 12 are “off”, consequently voltage node 26 LOW, i.e. ground. Since Q 6 20 “off” Q 5 18 “on” voltage output (OUT) 28 HIGH (“1”). When A 22 B 24 are LOW (“0”+“0”), Q 3 14 Q 4 16 are “off”, Q 1 10 Q 2 12 are “on”, consequently voltage node 26 HIGH. Since Q 5 18 “off” Q 6 20 “on” voltage output (OUT) 28 LOW, ground (“0”). When A 22 (or B 24 ) HIGH B 24 (or A 22 ) LOW (“1”+“0”), Q 3 14 Q 2 12 are “on”, Q 1 10 Q 4 16 are “off”, consequently voltage node 26 HIGH voltage output (OUT) 28 LOW, ground (“0”). The truth table 30 for above operations seen same that AND gate.

Although logic gates this design are backbone digital electronic processing, they suffer several disadvantages. It requires numerous FETs (six example FIG. 1) comprise logic gate cell, therefore cell occupies large area chip. Furthermore, result Boolean process not stored must synchronized with clock cycle used next operating step, or must sent separate storage cell for later recall. The above discussion was presented for complimentary metal oxide silicon (CMOS) logic devices. The transistor—transistor logic (TTL) family based bipolar transistors, but similar conclusions apply. In other words, cell single TTL logic gate comprised several transistors several resistors, uses considerable space chip. It apparent that it would desirable integrate functions logic operation storage single element.

SUMMARY OF THE INVENTION

Accordingly, there significant need for improved FETs similarly operating logic devices that used easily reliably high density memory logic environments.

An object present invention therefore provide novel hybrid FET structure that used memory element for nonvolatile storage digital information, well other environments (including, for example, logic applications for performing digital combinational tasks, or magnetic field sensor).

According first embodiment present invention, novel FET describing using ferromagnetic materials for source drain, described “spin injected FET.” This spin injected FET two operating stable states determined by gate voltage, “off” “on”. The first (e.g. source) second (e.g. drain) ferromagnetic layers this new FET are both fabricated magnetically anisotropic so permit device two stable magnetization states, parallel antiparallel. In “on” state spin injected FET two settable resistance states determined by relative orientation magnetizations ferromagnetic source drain, “HIGH” (antiparallel) “LOW” (parallel). One ferromagnetic films (source) fixed with large magnetic coercivity polled one direction other ferromagnetic film (drain) smaller coercivity. An external magnetic field change magnetization state device by orienting magnetization drain parallel or antiparallel relative that source.

In magnetic sensor embodiment present invention, spin injected FET incorporated “read” head for reading digital magnetic recorded data.

In memory storage element embodiment, spin injected FET provided having conductive write layer for carrying write electric current inductively coupling write magnetic field associated with this write current second (drain) ferromagnetic film. An external current generator change magnetization state drain, therefore, by inductively coupling magnetic field drain. Even if power removed above device, second ferromagnetic film orientation retained its set state, thus causing spin injected FET behave non-volatile memory element because two states magnetization orientation said second ferromagnetic layer correspond data values stored said memory element. An array spin injected FETs coupled together array form spin injected FET memory array.

The present spin injected FET therefore find application basic storage element integrated arrays nonvolatile random access memories (NRAM), may replace DRAM direct access memory (such magnetic disk drives) applications. The present spin injected FET invention substantial improvement over prior memory cell elements. Compared with DRAM, spin injected FET only single element cell permitting memory cell made smaller, memory nonvolatile not susceptible errors induced by background radiation (i.e. it radiation hard). Compared other nonvolatile memory cells, spin injected FET only single element, permitting cell size smaller, cell automatically isolated array unless it addressed, memory array compatible with existing CMOS (or other semiconductor) technology.

Further according another embodiment present invention, logic gate fabricated using spin injected FET. This logic gate implement any desired combinational task (function) relating one or more inputs spin injected FET output thereof. Depending particular function implemented, state logic gate (which determined by magnetization state drain) first set using magnetic field generated by current pulse transmitted write line inductively coupled ferromagnetic drain. This same wire also inductively couples magnetic field generated by combined current one or more input data signals spin injected FET. The ferromagnetic drain magnetization configured change or retain its orientation, depending particular combination input data signals corresponding boolean operation desired. In other words, ferromagnetic drain magnetization may read out output binary “1” or “0” corresponding some Boolean process dependent data input signals.

In any specific logic function embodiment, therefore, present invention configured implement function any following gates: NOR gate, NOT gate, NAND gate, OR gate AND gate, or more generally any logic gate implementing combinational task relating one or more combination inputs/outputs. The present spin injected FET invention substantial improvement over prior logic gates using semiconductor transistors [ordinary FETs for CMOS or bipolar transistors for TTL]. The spin injected FET requires fewer elements per logic cell, so cell size reduced packing density increased. The result each processing step stored nonvolatile state device read out any later time, without synchronization clock cycle. In this way, parallel processing by several logic gates facilitated. Furthermore, although basic ideas are presented herein for two-state device, appropriate for binary processing, it possible fabricate ferromagnetic layer with more than two stable magnetization states. Therefore, more generally n-state device fabricated, simultaneous processing n bits by each logic gate possible.

Furthermore, contrast prior art Datta Das spin transport device described above, spin injected FET present invention employs one ferromagnetic layer (source) with fixed magnetization orientation second ferromagnetic layer (drain) with magnetization whose orientation changes between two stable configurations: parallel or antiparallel with magnetization orientation source. The invention then uses memory effect associated with hysteresis ferromagnetic layer drain order create spin injected FET memory element or logic gate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematic top view prior art “spin injection” all metal transistor that makes use spin polarized electron current;

FIG. 2 schematic cross-sectional view prior art FET current modulator using ferromagnetic films

FIG. 3 schematic representation logical AND gate cell comprised conventional semiconductor field effect transistors (FETs), accompanying truth table;

FIG. 4 schematic cross-sectional view spin injected FET constructed accordance with teachings present invention;

FIG. 5 includes number density state diagrams describe charge spin transport limit where two ferromagnetic electrodes are separated by length L that same order electron mean free path 1 , where spin accumulation ˜M negligible;

FIG. 6A top view typical physical implementation spin injected FET illustrated FIG. 4;

FIG. 6B further cross-sectional view spin injected FET illustrated FIG. 4;

FIG. 7A schematic cross-sectional view further embodiment present invention including spin injected FET which operates memory cell, inductively coupled write line used for writing logical data value this cell;

FIG. 7B schematic cross-sectional view further embodiment present invention including memory array having spin injected FETs operating single memory cells, sense circuit that used for reading logical data value stored single cell;

FIG. 7C schematic plan view another embodiment present invention which includes array spin injected FET memory cells sense circuit that common number cells array;

FIG. 8 schematic view further embodiment present invention which includes spin injected FET used logic gate readout circuit that used therewith.

DETAILED DESCRIPTION OF THE INVENTION

The present invention makes use spin polarized electron transport ferromagnetic—non ferromagnetic interfaces, phenomenon which well known art. Further details this topic found above mentioned articles journals, well Johnson, Phys. Rev. Lett. 70, 2142 (1993), all which are incorporated by reference herein. Moreover, further details structure operation general bipolar magnetic spin transistor shown FIG. 4 can, found above reference pending applications Ser. Nos. 08/425884 08/493815, which are also incorporated by reference herein.

Spin Injected FET Memory Element

A preferred embodiment invention illustrated FIG. 1. A spin injected FET 100 created applying spin injection techniques high mobility semiconductor system (refer FIG. 4). A ferromagnetic film F 1 110 source S provides spin polarized carriers high mobility channel 112 , conductance which determined by gate voltage, V G 114 . A ferromagnetic film F 2 116 drain D presents spin sensitive impedance current flow, so that device conductance high when magnetizations ^M s ^M d source drain are aligned parallel low when ^M s ^M d are antiparallel. If magnetization 118 one films, e.g. F 1 , set “up” orientation [left right FIG. 4, i.e., direction substantially perpendicular axis channel 112 ], then resistance device two distinct states determined by magnetization orientation 120 F 2 : “up” (pointing right, equivalently LOW or “0”) or “down” (pointing left, equivalently HIGH or “1”) corresponds LOW or HIGH channel resistance source drain (or vice versa). Thus, FET 100 used non-volatile memory element. Moreover, it apparent skilled artisans that through use selected materials, magnetization orientation 120 general set any one n distinct states, thus permitting logical data item having n possible unique values stored memory element.

A logical data value (such binary bit value corresponding 0 or 1) written by using magnetic fields current pulses overlaid write lines (illustrated more detail FIG. 7A), orient ^M d either up or down. The stored information nonvolatile, isolated array because conductance channel also two states: approximately zero conductance (infinite impedance) “off” state when no gate voltage applied (e.g. for enhancement mode FET), high conductance “on” state when suitable voltage applied gate.

The stored bit read by sending read voltage pulse 114 gate 122 , addressing element by raising conductance channel setting FET “on” state, biasing source 190 with read voltage V R 124 , then sensing source-drain conductance, discriminating between two values that differ because spin-dependent conductance (resistance) drain.

The variable (2 state) resistance FET therefore used indicate presence logical “1” or “0” data bit stored state FET. The variable resistance FET explained modeled by following analysis: If ferromagnetic films F 1 118 F 2 120 are spaced (edge edge) within distance L order few electron mean free paths l, L˜l, if spin accumulation effects are weak (˜M small), then current transport geometry FIG. 4 described by density state diagrams FIG. 5. Typical values l are order 0.1 micron, preferred value L order 1 micron. For case negligible spin accumulation, difference resistance for cases where ^M 1 ^M 2 are parallel, R par , where ^M 1 ^M 2 are antiparallel, R anti , relative total resistance between F 1 F 2 , R ave , equal to:

R anti −R par =(2η 2 *R av )/(2−η 2 )

where η polarization efficiency F 1 F 2 . This result also assumes that L smaller than spin-flip mean free path Λ=ν F *T 1 , where ν F Fermi velocity T 1 mean time that electron remains polarized within channel.

For case that N conducting channel FET or 2 dimensional electron gas (2DEG), results expressed above describe channel resistance whose value depends relative orientation magnetizations ferromagnetic films, this variable resistance useful for implementing spin injected FET memory cell or logic gate.

A more detailed look structure preferred embodiment spin injected FET, where spin injection incorporated into enhancement mode FET, depicted top view FIG. 6A cross-sectional view FIG. 6B. Two regions high conductance material 212 having approximate thickness 100 nm are incorporated into surface p-type silicon substrate 204 . The high conductance material highly n-doped region Si, metallic or polysilicon layer, epitaxial layer high mobility semiconducting material [such InAs], metallic layer diffused into doped region substrate, or any other material with similar electrical properties. One function high conductance layer 212 diminish (or eliminate) Schottky barrier that typically exists interface between (ferromagnetic) metal semiconductor, thereby improve ohmic contact between source 220 (or drain 230 ) conducting channel 208 . By improving Ohmic contact, spin transmission between source 220 (or drain 230 ) channel 208 are enhanced (i.e. value η increased). Another function high conductance layer 212 shorten length L c channel 208 . Thus, source 220 drain 230 may separated, edge edge, by 1 micron, high conductance layer may extend 0.2 micron edge source 220 drain 230 so that length channel reduced L c =0.6 micron. Finally, it understood those skilled art that high conductance layer 212 most effective silicon based devices. There are alternative materials systems, such Indium Arsenide—Indium Antiminide heterostructures, where ohmic contact between ferromagnetic source 220 (or drain 230 ) channel ( 208 ) intrinsically good no highly conducting layer required. Even silicon based devices, highly conducting layer not theoretically necessary, but it likely that its presence enhances device performance by important measure. In other words, it likely that Schottky barrier randomizes spin orientation polarized current so effectively that resulting polarization values are so small make device impractical.

An insulating layer 202 (silicon dioxide, polyimide, etc.), 40 nm thick coats portion p-type silicon substrate 204 , overlapping portion conductive material 212 . A thin film highly conducting material 206 (metal or polysilicon) approximately 0.7 microns wide fabricated over insulator thickness 60 nm operate gate: this embodiment, positive voltage applied gate draws charge carriers surface substrate increases conductivity channel 208 near insulator—substrate interface, beneath gate, allowing current flow between two high conductance regions 212 when bias voltage applied between source 220 drain 230 . Those skilled art appreciate that this essentially same gating operation that typically used enhancement mode FET, where high conductance regions are doped, n-type silicon. Moreover, while preferred embodiment shown enhancement mode FET, it apparent those skilled art that present invention used with any general FET geometry, including those having lightly doped source/drains, vertical topologies, etc.

A second insulating layer 210 , deposited thickness approximately 50 nm covers gate isolate it during subsequent processing steps. A thin ferromagnetic film 220 [e.g. permalloy, cobalt, iron Heusler alloy or Fe 0.5 Co 0.5 ] which 60 nm thick (film 220 may coated by 10 nm thick layer nonmagnetic metal, such Ti or Au, order prevent oxidation) deposited one side gate making ohmic contact with highly conductive layer 212 region via hole 222 . This film 220 considered ferromagnetic “source” spin injected FET. A metallic strip 224 (or similar conductor) approximately 100 nm thick overlaps ferromagnetic film 220 also connected read or bias line. As described above, ferromagnetic source 220 chosen [by choice material, exchange bias, or induced magnetic anisotropy] relatively large coercivity H c,1 with easy magnetization axis parallel ^z. During device operation, magnetization set initially up orientation [or, alternatively, down] along +^z, magnetization source 220 typically remains that orientation during all device operations. The shape source 220 FIG. 6A chosen crescent so that fringe fields magnetic poles ends film are kept far gate region. Those skilled art appreciate that other geometries that minimize stray fields region gate work equally well.

A second thin ferromagnetic film 230 [of permalloy, cobalt, Fe 0.5 Co 0.5 , etc.] deposited thickness 70 nm other side gate making ohmic contact with highly conductive medium region via hole 232 . This film 230 considered ferromagnetic “drain” spin injected FET. A metallic strip 234 (similar composition thickness strip 224 ) overlaps ferromagnetic film 230 also connected bit line. Ferromagnetic drain 230 chosen [by choice material or induced magnetic anisotropy] small coercivity, H c,2 <H c,1 , with relatively easy axis parallel ^z.

As seen FIG. 6A, preferred embodiment, ferromagnetic film 220 (source) and/or ferromagnetic film 230 (drain) are formed with asymmetric shape. The shape ferromagnetic layers symmetric about x-axis, asymmetric about z-axis; latter, explained above, represents easy axis magnetization. The ferromagnetic elements may also include both convex portion concave portion represented by right side left side curved sections such elements, well straight portions. The curved sections are preferably aligned along asymmetric or easy axis. As further seen FIG. 6A, convex portion ferromagnetic element 230 preferably situated so opposite convex portion ferromagnetic element. Again preferred embodiments element 220 larger coercivity also physically larger than element 230 which turn lower coercivity so that it changed response write signal.

During device operation, orientation magnetization drain set by overlaid set write lines, depicted schematically FIG. 7A. In write procedure, sending write current pulse 310 positive [negative] polarity magnitude 2 mA down write line 312 (located approximately 50 nm away drain 116 ) generates magnetic field 314 drain 116 orients (sets) magnetization state 120 drain up (or down), parallel (or anti-parallel) relative orientation 118 source 110 . While write line described “line” it understood by persons skilled art that any number well-known structures capable carrying sufficient current (including for example conductive film, or interconnect line) generate field H suitable present invention. Moreover, while not essential description present invention, additional details concerning operation read/write lines connection with ferromagnetic layers found aforementioned pending application Ser. Nos. 08/425884 08/493815.

Under these conditions therefore, spin injected FET two settable stable states, determined by whether magnetization orientation 118 drain 116 up or down (parallel or anti-parallel relative magnetization orientation 120 source 110 ), which states correspond stored “bit” data (i.e, 0 or 1). Moreover, when no voltage applied gate 122 , channel 112 high electrical impedance [e.g. for enhancement mode FET] no spin polarized current flow source 110 drain 116 . The stored bit information thus nonvolatile, isolated memory array by high resistance channel 112 .

In read process, positive voltage V G 114 applied gate 122 , channel 112 relatively high conductance bias voltage V R 124 causes current flow source 110 drain 116 . The electric current which flows comprised spin polarized electrons which enter highly conductive material 212 (refer FIG. 6B). Since dimensions highly conducting material 212 , extending about 0.2 micron past edge source 220 thickness about 0.1 micron, are much smaller than characteristic spin diffusion length δ s,1 (estimated about 1 micron) highly conductive material, current that enters channel 208 retains large fraction its initial spin polarization. Furthermore, preferred orientation magnetization source along +^z (or −^z); injected spins oriented along ^z axis not precess under influence gate voltage V G ( 114 FIG. 7A). The presence or lack precession (more accurately, enhanced versus diminished precession) operational difference between Datta/Das device present invention. As described above, electronic source-drain conductance two different values for two different states (0 or 1) device, with parallel or antiparallel magnetization orientation, so quantity spin polarized current which flows function this conductance. The readout operation completed by sensing source-drain conductance discriminating between two possible current values. It apparent those skilled art that ferromagnetic drain (or source) fabricated with n stable magnetization states, operation 2-state device described herein generalized operation n-state device.

An example sensing logical data state spin injected FET used single element memory cell, depicted FIG. 7B. Source 110 connected common read [or bias] line terminal 354 , gate 122 common word line terminal 364 , drain 116 common bit line terminal 374 . At end bit line sense circuit 380 which compares readout cell with reference voltage [internally or externally supplied]. A word line voltage applied gate terminal 364 selects cell for reading. A read line voltage simultaneously applied source terminal 354 . As suggested above source—drain current one two values, determined by two conductance values spin injected FET series with resistance R 390 end bit line. These two current values turn develop two different voltage values top 384 resistor 390 input 386 sense amplifier 380 . This voltage value compared with reference voltage thus logical value stored cell interpreted logical “1” or “0.”

To form memory array, number spin injected FET memory cells configured depicted FIG. 7C. Here each spin injected FET drawn with symbol for conventional semiconductor FET with additional arrow representing variable resistance value, referring two resistance values when FET “on” state. Write line 312 included for each spin injected FET, symbol, side drain. A single sense circuit 380 common for all cells array. Each cell isolated array, its value sensed only when addressed. For example, cell 400 sensed only when addressed by pulse applied its gate 122 . Finally, while not shown or discussed explicitly herein, it apparent those skilled art that additional peripheral support circuits commonly associated with semiconductor memory arrays (decoders, buffers, latches, equalization, precharge, etc) easily adapted for use with present invention.

The spin injected FET improvement over DRAM because memory cell single element so that packing densities greater. It also superior signal noise ratio, memory nonvolatile so that array draws substantially less power. The spin injected FET improvement over other nonvolatile technologies because cell simpler, packing densities are greater, signal noise superior, isolation array more efficient.

The device may also used field sensor, e.g. recording head. Note that readout voltage increased by varying parameters such type ferromagnetic material thickness. For example, iron films approximately twice saturation magnetization permalloy, substituting iron for permalloy would double magnitude readout voltage.

Spin Injected FET Logic Gate

Boolean logic processes also performed using present spin injected FET. For example, logic input having two logical data values represented by two different current levels data wire. This logical input (having particular current level corresponding “1” or “0”) combined with second logical input (also having current level corresponding either “1” or “0”), combined sum current levels these logical inputs then applied write line coupled magnetically ferromagnetic layer FET (source or drain). The sum these logic inputs constitutes write current pulse write line corresponding magnetic field acts inductively magnetization state ^M ferromagnetic layer. Depending state orientation ^M ferromagnetic layer, particular combination inputs therefore, magnetic field write current pulse may alter this orientation, thus “storing” result logic operation form new magnetization orientation ferromagnetic layer. Again, while not essential description present invention, additional details concerning structures circuits usable connection with magnetic spin transistor boolean logic processing devices found aforementioned pending application Ser. No. 08/493815.

Those skilled art appreciate that this principle extended create N input logical AND gate or similar logic processor. For example, logic processing device implemented wherein magnetization state drain FET set so that it only altered when all N inputs are “high” current level, thus generating sufficiently high magnetic field change orientation FET ferromagnetic layer. Other configurations for adapting other boolean processes readily apparent skilled artisans.

The result automatically stored boolean function data value read out any later time. In this way spin injected FET function logic gate with memory capability. If readout operation enables result (“0” or “1”, HIGH or LOW) transmitted another gate for another operation, then gates linked together perform combinational tasks digital processing. An example appropriate readout technique presented FIG. 8. Readout circuit 410 amplifies output appropriate CMOS level (HIGH or LOW) so that it integrated with CMOS (or, for appropriate circuit, TTL) logic. Alternatively, output sent write line another spin injected FET gate.

The example presented for case n-channel enhancement mode spin injected FET. Other devices (depletion mode, p-channel, etc.) fabricated incorporating ferromagnetic layers constructed operated similar way readily apparent those skilled art. As seen FIG. 8, spin injected FET 400 two resistive values “on” state, R s =R′+/−ΔR. In real MOSFET device, R′ may typically value R′=100 Ω, spin dependent resistance may vary by 15% so that R s =85, 115 Ω are LOW HIGH resistive values device. Typically readout resistor R 390 would matched value R′, bias voltage would value V DD =15 Volts. In readout circuit 410 , FET Q 1 412 p-channel enhancement mode FET whose body biased relatively high value, V 1 =8.1 Volts. FET Q 2 414 n-channel enhancement mode FET whose body biased relatively low value, V 2 =7.0 Volts. The bias provided by external voltage source, appropriate doping or other methods known art.

When R s LOW (85 Ω), voltage input node 416 readout circuit 410 relatively HIGH (8.1 V). In this situation, Q 1 412 “off”, Q 2 414 “on” output 418 clamped LOW (ground). When R s HIGH (115 Ω), voltage input 416 readout circuit 410 relatively LOW (7.0 V). In this case, Q 1 412 “on”, Q 2 414 “off” output 418 clamped HIGH (V DD ). Readout circuit 410 thus functions convert input levels conventional CMOS output values (GND V DD ).

When elements FIG. 8 are considered single logic function (AND) gate, number constituent elements three, only half size typical CMOS gate, therefore packing densities logic gates increased. The result logic operation automatically stored nonvolatile state. Since no additional memory cell needed store result, further increases density (and operating speed) are achieved. Furthermore, it possible associate single readout driver circuit with several spin injected FETs. Each latter perform simple programmed Boolean operation store result non-volatile manner. At any desired time, results these operations called any sequence. Thus, spin injected FET function general purpose element programmable logic array, or gate array. Again, typical support circuits known art associated with such programmable logic arrays used augment enhance performance circuits embodying present invention.

Although present invention been described terms preferred embodiment, it apparent those skilled art that alterations modifications may made such embodiments without departing teachings present invention. For example, while not shown or discussed explicitly herein, it apparent those skilled art that additional peripheral support circuits commonly associated with semiconductor memory arrays (decoders, buffers, latches, equalization, precharge, etc) easily adapted for use with present invention. Moreover, while preferred embodiment shown enhancement mode FET, other active devices (depletion mode, p-channel, etc.) fabricated using well known techniques include teachings present invention.

Furthermore, other suitable FET orientations geometries, including those having lightly doped source/drains, vertical topologies, etc. used with present invention.

In addition, it apparent those skilled art that device constructed stacked fashion, i.e., having multiple levels memory cells or logic gates present invention. This accomplished merely by adding passivating layer or similar insulating layer between such levels, along with appropriate conventional interconnect peripheral support circuits. Thus, device constructed this manner even greater integration advantages over prior art.

Accordingly, it intended that all such alterations modifications included within scope spirit invention defined by appended claims.