MRAM and data writing method therefor

What claimed is:




1. A Magnetic random access memory (MRAM), comprising: first wiring through which write current caused flow one direction; selecting transistor having first electrode connected first wiring second electrode connected power voltage potential supply node for controlling write current; plurality magnetic memory cells each arranged first wiring, one end plurality magnetic memory cells being connected first wiring.


2. The memory claimed 1, wherein other end plurality MRAM cells are connected second wiring through which current caused flow both directions.


3. The memory claimed claim 2, wherein first wiring first sub-wiring, first sub-wiring connected first main wiring directly, not through transistor, second wiring second sub-wiring, second sub-wiring connected second main wiring through transistor.


4. A MRAM, comprising: main bit line; sub-bit line having one end connected said main bit line; main word line; sub-word line having one end connected said main word line; MRAM cell provided between said sub-word line said sub-bit line; select transistor coupled other end one said sub-word said sub-bit lines.


5. The MRAM claimed claim 4, wherein substrate current said select transistor becomes write current which flows through one sub-bit line sub-word line.


6. The MRAM claimed claim 5, wherein substrate current based snap back phenomenon which caused occur by applying breakdown voltage drain said select transistor.


7. The MRAM claimed claim 5, wherein write current current generated when electric charge accumulated electrostatic capacity discharged, which accompanies one said main bit sub-bit lines said main word sub-word lines.


8. A MRAM, comprising: plurality first sub-row lines extending first direction; plurality first sub-column lines extending second direction different first direction; first memory cell array including plurality first magnetic memory cells each arranged crossing points between corresponding one said first sub-row lines corresponding one said first sub-column lines; plurality second sub-row lines extending first direction; plurality second sub-column lines extending second direction; second memory cell array including plurality second magnetic memory cells each arranged crossing points between corresponding one said second sub-row lines corresponding one said second sub-column lines; plurality third sub-row lines extending first direction; plurality third sub-column lines extending second direction; third memory cell array including plurality third magnetic memory cells each arranged crossing points between corresponding one said third sub-row lines corresponding one said third sub-column lines; plurality main row lines provided common said first second memory cell arrays; plurality main column lines provided common said first third memory cell arrays, wherein each plurality first sub-row lines first memory cell array two end portions, one two end portions connected one main row lines, other end portion two end portions connected first row selecting transistor, each plurality sub-column lines first memory cell array two end portions, one two end portions connected one main column lines through column selecting transistor, other end portion two end portions connected write circuit.


9. The MRAM claimed claim 8, wherein predetermined write current caused flow through one sub-row lines during write operation current generated when predetermined signal supplied row selecting signal line row selecting transistors make one row selecting transistors get conducting state discharge electric charge previously accumulated electrostatic capacity one main row lines sub-row lines.


10. The MRAM claimed claim 9, wherein conducting state row selecting transistor state which current caused flow drain row selecting transistor substrate.

BACKGROUND OF THE INVENTION

1. Field Invention

The present invention relates magnetic random access memory (MRAM) data writing method therefor.

2. Related Background Art

In recent years, MRAM which highly densely integrated magnetic substances substrate memory cells, which nonvolatile characteristics, high speed operation repetition resistance magnetic recording, been expected next generation memory.

FIGS. 7A 7B are perspective views each useful explaining basic structure operation memory cell MRAM.

As shown FIG. 7A, MRAM cell includes pinned layer 12 made ferromagnetic film having fixed magnetization direction, insulating film 13 data storage layer 14 made ferromagnetic film. The MRAM cell provided between lower wiring 11 upper wiring 15 .

FIG. 7B perspective view useful explaining operation for writing reading out data memory cell shown FIG. 7A.

The storage data carried out by utilizing “magneto-resistance effect” which resistance value insulating film changed by 30 40% between state which directions magnetization pinned layer 12 data storage layer 14 are “parallel” each other (corresponding data 0 ) state which directions magnetization pinned layer 12 data storage layer 14 are “anti-parallel” each other (corresponding data 1 ). For this storage, direction magnetization data storage layer 14 changed by external magnetic field generated by causing predetermined current through upper wiring 15 lower wiring 11 thereby store binary digit data, for example.

The operation for reading out data memory cell follows: A predetermined potential difference applied across upper wiring 15 lower wiring 11 cause tunneling current 16 . This tunneling current 16 penetrates through pinned layer 12 , insulating layer 13 data storage layer 14 caused flow lower wiring 11 upper wiring 15 . Thus, data read out memory cell. That say, resistance value insulating film 13 changed due tunnel magneto-resistance effect when directions magnetization two ferromagnetic layers 12 14 sandwiching therebetween insulating layer 13 are parallel or anti-parallel each other. Then, this change current detected thereby read out data stored memory cell outside.

FIG. 8 schematic view useful explaining write operation MRAM which memory cells shown FIGS. 7A 7B are arranged array.

Here, description hereinbelow given with respect case where data written memory cell MC. Predetermined currents (write currents C 1 C 2 ) are selectively caused flow through word line W 112 bit line B 152 time when data intended written memory cell MC regulate magnetic domains (domains) data storage layer memory cell MC one direction by utilizing composite magnetic field M 12 obtained by composing magnetic fields (magnetic fields M 1 M 2 ) induced circumference wirings. Thus, operation for writing data memory cell MC realized.

On other hand, for storage inverted data memory cell MC, direction current caused flow through one word line W 112 bit line B 152 , e.g., bit line B 152 selectively inverted with respect above-mentioned case operation for writing data memory cell MC. Thus, direction magnetic field M 2 changed by 180 degrees change direction composite magnetic field M 12 by 90 degrees, whereby domains data storage layer memory cell MC are forcibly inverted. As result, “parallelism” “anti-parallelism” direction domains pinned layer data storage layer realized by utilizing external magnetic field.

As described above, MRAM memory cell array, current caused flow through memory cell crossing point between selected word line bit line detected judge storage state. However, if scale memory cell array itself increased, then wiring resistances wiring capacities word lines bit lines are increased according. As result value detected current caused flow when data read out memory cell becomes small or delay response when data read out therefrom increased.

In particular, since memory cell constituted by insulating film, which about 2 nm thick, sandwiched between ferromagnetic films two layers, for main component wiring capacity, capacity due memory cell connected wirings larger than that wirings themselves. Thus, if number memory cells connected wirings increased, then wiring capacity increased proportion thereto.

In order avoid such problem, there conventionally been taken measures that, for example, upper limit set wiring resistance so that current level when reading out data memory cell does not become smaller than predetermined value, wiring length limited order avoid increase wiring capacity limit scale memory cell array, so forth.

However, MRAM capacity increased, scale memory cell array increased. Thus, this problem gradually become important.

In order cope with such problem, proposal dividing memory cell array been made.

FIG. 9 schematically shows such configuration, circuit diagram showing sub-memory cell array constituted by sub-word lines SW 1 SWm sub-bit lines SB 1 SBn.

The sub-word lines SW 1 SWm constituting sub-memory cell array are connected main word lines W 1 Wm through sub-word line selecting transistors WT 1 WTm, respectively. The sub-bit lines SB 1 SBn are connected main bit lines B 1 Bn through sub-bit line selecting transistors BT 1 BTn, respectively. In such manner, memory cell array configured form hierarchical structure main bit lines main word lines, sub-bit lines sub-word lines (refer JP 2002-170379 A (FIG. 1) for example).

As described above, MRAM high performance such high speed rewriting reading. However, other hand, since time when data intended written, currents are caused flow through corresponding ones wirings generate induced magnetic fields, relatively large write currents, i.e., write currents several milliamperes are required per memory cell. If method dividing conventional memory cell array into blocks introduced order avoid above-mentioned problem, there may encountered problem described below. The division cell array, described above, adopts hierarchical structure having main bit lines main word lines distributed so cover whole cell array, sub-bit lines sub-word lines distributed only within each blocks (sub-cell arrays). Then, normal MOS transistors are required switching elements for changing main bit lines main word lines over sub-bit lines sub-word lines. Such switching elements are formed each blocks obtained by division change main bit lines main word lines over sub-bit lines sub-word lines, respectively. In MRAM, ability cause current milliampere level flow required for MOS transistor switching element correspondence current when data written. As well known, MOS transistor cause current magnitude which proportional width (W) gate electrode, but inversely proportional length (L) thereof flow therethrough. Hence, if size ratio length width gate electrode determined, moreover, certain design conditions are determined for MOS transistor switching element, then absolute values length width gate electrode which are required inevitably determined therefrom. Usually, ratio W L needs set fall within range about 10 50 order cause current several milliamperes flow. Thus, for example, if MOS transistor device with L 0.2 μm intended formed, then W must 2 10 μm.

SUMMARY OF THE INVENTION

In light foregoing, it is, therefore, object present invention provide magnetic memory (MRAM) having memory cells formed using tunnel magneto-resistance elements (TMR elements) which capable realizing novel array structure, operation thereof, more miniature planar layout.

According one aspect present invention, there provided MRAM including: first wiring through which write current caused flow one direction; selecting transistor provided downstream side write current first wiring; plurality MRAM cells provided upstream side with respect position where selecting transistor provided first wiring. The other ends MRAM cells are connected second wiring through which current caused flow both directions. The first wiring first sub-wiring which connected first main wiring directly, not through transistor, second wiring second sub-wiring which connected second main wiring through transistor. The first second main wirings are main bit line main word line, respectively, first second sub-wirings are sub-bit line sub-word line, respectively.

More specifically, according present invention, MOS transistor switching transistors switching elements memory cell array are arranged inversely with respect conventional arrangement (refer FIG. 9), i.e., they are arranged only end portions sub-memory cell array. Then, main bit line sub-bit line, or main word line sub-word line are directly connected each other. The switching transistor arranged so meet arrangement order main bit line, sub-bit line switching transistor connected series with each other. Since current conducting state switching transistor controlled with current caused flow through this series-connected elements, selection sub-memory cell array becomes possible. In addition, according present invention, operation switching transistor, unlike above description prior art, channel current depending both width length gate electrode not utilized, but current (substrate current) caused flow drain diffusion layer semiconductor substrate utilized. A so-called snap back current which caused flow by applying voltage near breakdown voltage drain may utilized substrate current. In other words, operation principles when turning ON switching transistor utilizes junction breakdown drain electrode, or current caused flow direction drain electrode substrate, irrespective presence or absence channel formation owing gate electrode normal MOS transistor.

As described above, present invention, since selecting transistor provided downstream side wiring, write current prevented being regulated by channel current selecting transistor. More specifically, present invention, channel current switching transistor not used, but substrate current utilized. Therefore, large current caused flow with small transistor area without depending ratio width W length L channel. As result, according present invention, it possible reduce area memory cell array.

Moreover, present invention, normal D.C. current not steadily caused flow. Instead, electric charges are accumulated electrostatic capacities main bit lines, electric charges thus accumulated therein are discharged all once form discharge current by turning ON switching transistor. Then, data may written memory cell by utilizing discharge current.

In present invention, predetermined write currents are caused flow through word line bit line, respectively, induce magnetic fields circumference word line bit line, whereby binary digit data 0 or 1 stored memory cell located crossing point between word line bit line basis induced magnetic fields.

The memory cell present invention storage element which constituted by magneto-resistance element having least three layers including first second magnetic thin films, insulating film sandwiched between first second magnetic thin films, which serves store therein binary digit data 0 or 1 accordance with change tunnel electrical resistance insulating film. At this time, this change tunnel electrical resistance insulating film depends whether directions magnetization first second ferromagnetic thin films are parallel or anti-parallel each other due change magnitude external magnetic field.

A word line selecting transistor bit line selecting transistor present invention are MOS transistors (of n-type, for example), their gate electrodes are connected word line selecting signal line bit line selecting signal line controlled accordance with word line selecting signal bit line selecting signal, respectively. The MRAM present invention may write circuit read circuit which are common plurality sub-memory cell arrays. It more desirable unit for synchronizing timings which switching transistors are turned ON so that write currents are simultaneously caused flow through word line bit line. It more desirable adopt structure with which drain diffusion layer switching transistor relatively low breakdown voltage.

According present invention, there provided data writing method for MRAM including TMR cells, which data written corresponding one TMR cells using snap back current.

According present invention, there provided data writing method for MRAM including TMR cells, including steps accumulating electric charges electrostatic capacity one word lines bit lines, discharging accumulated electric charges form discharge current write data one TMR cells using discharge current.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 circuit diagram showing MRAM according first embodiment present invention;

FIG. 2 diagram schematically showing operation selecting transistor WT shown FIG. 1;

FIG. 3 graphical representation useful explaining write current device shown FIG. 1;

FIG. 4 circuit diagram showing MRAM according second embodiment present invention;

FIG. 5 circuit diagram showing MRAM according third embodiment present invention;

FIG. 6 circuit diagram showing MRAM according fourth embodiment present invention;

FIGS. 7A 7B are perspective views useful explaining structure MRAM cell storage operation thereof;

FIG. 8 schematic view useful explaining method writing data MRAM cell;

FIG. 9 circuit diagram showing conventional MRAM cell array.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 circuit diagram showing sub-memory cell array SMA 1 MRAM according first embodiment present invention.

The sub-memory cell array SMA 1 includes plurality main word lines W 1 Wm (m: natural number equal or larger than 2), plurality main bit lines B 1 Bn (n: natural number equal or larger than 2). The main word lines W 1 Wm are distributed so intersect main bit lines B 1 Bn.

Sub-word lines SW 1 SWm are distributed parallel with main word lines W 1 WM, respectively. One ends sub-word lines SW 1 SWm are connected corresponding main word lines W 1 Wn, respectively, other ends thereof are connected corresponding one ends (corresponding drain terminals) word line selecting transistors WT 1 WTm for selecting one word lines sub-memory cell arrays, respectively. All gates word line selecting transistors WT 1 WTm are connected first word line selecting line WSL 1 . A word line selecting signal which activated time when data intended written memory cell supplied word line selecting line WSL 1 . All other ends word line selecting transistors WT 1 WTm are connected ground line. In addition, other ends sub-word lines SW 1 SWm are connected corresponding one ends read transistors RT 1 RTm, respectively. All other ends read transistors RT 1 RTm are connected sense amplifier SA 1 . A read signal line RSL 1 which read signal supplied connected each gates read transistors RT 1 RTm.

Sub-bit lines SB 1 SBn are distributed parallel with main bit lines B 1 Bn, respectively. One ends sub-bit lines SB 1 SBn are connected corresponding main bit lines BT 1 BTn through bit line selecting transistors BT 1 BTn for selecting one bit lines sub-memory cell arrays, respectively. All gates bit line selecting transistors BT 1 BTn are connected first bit line selecting line BSL 1 . A bit line selecting signal which activated time when data intended written read out memory cell supplied bit line selecting line BSL 1 . All other ends sub-bit lines SB 1 SBn are connected write circuit K 1 . The write circuit K 1 includes first group transistors KD 1 KDn second group transistors KE 1 KEn. The first group transistors KD 1 KDn are controlled accordance with first write control line D 0 which activated time when write data goes level “1” for example which first write data control signal supplied. The second group transistors KE 1 KEn are controlled accordance with second write control line E 0 which activated time when write data goes level “0” for example which second write data control signal supplied.

The word line selecting transistors WT 1 WTn, bit line selecting transistors BT 1 BTn are constituted by MOS transistors respectively.

Next, operation cell array present invention hereinbelow described with reference FIG. 1. In this case, description now given with respect case where data written memory cell C 11 first sub-memory cell array SMA 1 .

First all, word line W 1 selected then selection signal inputted first word selecting line WSL 1 cause word line selecting transistors WT 1 conduct. All main word lines W 2 Wm other than selected word line W 1 are not selected. As result, sub-word line SW 1 connected main word line W 1 selected. Next, write current caused flow through main word line W 1 using constant current source (not shown) for example. The write current flows main word line W 1 word line selecting transistor WT 1 through sub-word line SW 1 . At same time, main bit line B 1 selected then selection signal inputted first bit selecting line BSL 1 cause bit line selecting transistor BT 1 conduct. All main bit lines B 2 Bn other than main bit line B 1 are not selected. As result, sub-bit line SB 1 connected main bit line B 1 selected. On other hand, write circuit K 1 , transistor KE 1 put into conducting state transistor KD 1 put into non-conducting state accordance with signal which suitably introduced. If under this state, write current supplied constant current source (not shown) caused flow through main bit line B 1 , then write current caused flow main bit line W 1 sub-bit line SB 1 through bit line selecting transistor BT 1 . On other hand, case where data different foregoing written memory cell C 11 , transistor KE 1 put into non-conducting state, transistor KD 1 put into conducting state. As result, write current caused flow sub-bit line SB 1 main bit line B 1 through bit line selecting transistor BT 1 .

At time when data intended written memory cell, current several milliamperes caused flow through corresponding one word line selecting transistors WT 1 WTm. In this case, for this current, channel current normal MOS transistor not utilized, but current b caused flow drain, i.e., terminal connected corresponding one sub-word lines SW 1 SWm substrate utilized (refer FIG. 2).

The characteristics such substrate current shown FIG. 3.

FIG. 3 shows characteristic curves relationship between drain voltage (V) (axis abscissa) MOS transistor drain current (A) thereof (axis ordinate), plotted for gate voltage parameter ranging 0 V 7 V. From these characteristic curves, it understood that while drain voltage kept low, channel current MOS transistor caused flow, but drain voltage becomes large, substrate current caused flow. It found out that when gate voltage becomes high, this phenomenon easy occur even if drain voltage relatively low. This phenomenon called so-called snap back phenomenon. The snap back phenomenon occurs due following process: By applying high voltage drain,

1. impact ionization occurs vicinity drain,

2. positive holes are caused flow into substrate,

3. source substrate are biased forward direction,

4. large number electrons are caused flow source into substrate,

5. impact ionization further occurs vicinity drain cause positive holes flow into substrate provide positive feedback state.

In short, snap back phenomenon, parasitic bipolar transistor source (emitter), substrate (base) drain (collector) caused conduct, breaking down source drain so that drain voltage reduced show negative resistance. In this phenomenon, generated voltage further reduced gate length becomes shorter. Moreover, if this phenomenon occurs, then current caused flow towards substrate. However, since this current not current caused flow through channel normal MOS transistor, even case small transistor, large current caused flow without being proportion ratio channel width channel length. For this reason, when present invention applied transistor for selecting word line or bit line, even with MOS transistor having layout relatively small area, large current caused flow.

For example, when data intended written memory cell C 11 , order that snap back phenomenon may caused occur selecting transistor WT 1 , voltage range 4.2 7.0 V, e.g., voltage 4.2 V applied main word line W 1 accordance with characteristics shown FIG. 3 cause write current flow therethrough. Also, predetermined voltage, e.g., voltage 4.2 V applied main bit line B 1 well. The above-mentioned voltages are applied form pulses word line selecting line WSL 1 bit line selecting line BSL 1 cause currents flow therethrough, respectively.

Other word lines bit lines which are not selected are grounded or voltage not allowing snap back phenomenon occur applied thereto so that no write current caused flow therethrough. From FIG. 3, for example, voltage which larger than 0 V, but smaller than 4.2 V corresponds voltage not allowing snap back phenomenon occur. In general, since withstanding voltage TMR element about 1.5 V, when voltage applied selected main word line main bit line 4.2 V, it more preferable apply voltage range 2.7 3.7 V word lines bit lines which are not selected. This voltage “a voltage not allowing snap back phenomenon occur”. Since if current concerned does not reach level required for magnetic inversion, then no disturbance caused TMR element, therefore such voltage set.

The description been given so far with respect method writing data memory cell C 11 crossing point between sub-word line SW 1 sub-bit line SB 1 .

When data read out memory cell, e.g., memory cell C 11 first sub-memory cell array SMA 1 , only main bit line B 1 selected apply thereto read voltage. The main bit lines other than main bit line B 1 are not selected.

A read current caused flow selected main bit line B 1 through sub-bit line SB 1 , memory cell C 11 , sub-word line SW 1 word line read selecting transistor RT 1 . Then, read current supplied sense amplifier SA 1 detected thereby.

FIG. 4 circuit diagram showing MRAM according second embodiment present invention.

FIG. 4 shows memory cell array MRAM present invention which plurality sub-memory cell arrays each shown FIG. 1 are arranged. While sub-memory cell arrays are arranged matrix, this embodiment, only sub-memory cell arrays SMA 1 SMA 3 are illustrated. The description respect giving detailed account sub-memory cell array SMA 1 shown FIG. 1 omitted here for sake simplicity.

The sub-memory cell array SMA 1 sub-memory cell array SMA 2 hold main word lines W 1 Wn common. The sub-memory cell array SMA 2 includes: main bit lines Bh Bj (h, j: natural number equal or larger than 2, n<h, h<j); sub-bit lines SB 21 SB 2 n distributed correspondence main bit lines Bh Bj; sub-word lines SW 21 SW 2 m distributed correspondence main word lines W 1 Wm; memory cells arranged crossing points between sub-word lines SW 21 SW 2 m sub-bit lines SB 21 SB 2 n. That say, sub-word lines SW 11 SW 21 hold main word line W 1 common. Thus, memory cells C 11 C 1 n sub-memory cell array SMA 1 memory cells C 1 h C 1 j sub-memory cell array SMA 2 hold main word line W 1 common. Moreover, sub-memory cell array SMA 2 includes: selecting transistors BT 2 h BT 2 j which are controlled so caused conduct through bit line selecting line BSL 1 ; selecting transistors WT 21 WT 2 m which are controlled so caused conduct through word line selecting line WLS 2 which activated time when data intended written memory cell; read line selecting line RSL 2 which activated time when data intended read out memory cell. Furthermore, sub-memory cell array SMA 2 , similarly sub-memory cell array SMA 1 , includes write circuit K 2 .

The sub-memory cell array SMA 1 sub-memory cell array SMA 3 hold main bit lines B 1 Bn common. The sub-memory cell array SMA 3 includes: main word lines Wg Wk (g, k: natural number equal or larger than 2, m<g, g<k); sub-word lines SW 3 g SW 3 k distributed correspondence main word lines Wg Wk; sub-bit lines SB 31 SB 3 n distributed correspondence main bit lines B 1 Bn; memory cells provided crossing points between sub-word lines SW 3 g SW 3 k sub-bit lines SB 31 SB 3 n. Moreover, sub-memory cell array SMA 3 includes: selecting transistors BT 31 BT 3 n which are controlled so caused conduct through bit line selecting line BSL 2 ; selecting transistors WT 3 g WT 3 k which are controlled so caused conduct through word line selecting line WSL 1 which activated time when data intended written memory cell; read selecting line RSL 1 which activated time when data intended read out memory cell.

Description hereinbelow given with respect operation for writing data memory cell C 11 sub-memory cell array SMA 1 .

The main word line W 1 selected, selection signal inputted first word line selecting line WSL 1 cause word line selecting transistor WT 11 conduct. Other main word lines W 2 Wm other than main word line W 1 are not selected. A non-selection signal inputted each word line selecting lines other than first word line selecting line WSL 1 make word line selecting transistors connected thereto get non-conducting state. As result, sub-word lines connected main word line W 1 , only sub-word line SW 11 selected. Then, when write current caused flow through main word line W 1 , write current then caused flow selected main word line W 1 selected sub-word line SW 11 , selected word line selecting transistor WT 11 . On other hand, concurrently therewith, main bit line B 1 selected, selection signal inputted first bit line selecting line BSL 1 cause bit line selecting transistor BT 11 conduct. Other main bit lines other than main bit line B 1 are not selected. Moreover, non-selection signal inputted each bit line selecting lines other than first bit line selecting line BSL 1 make bit line selecting transistors connected thereto get non-conducting state. As result, sub-bit lines connected main bit line B 1 , only sub-bit line SB 11 selected. Then, when write current caused flow through main bit line B 1 , write current then caused flow selected main bit line W 1 selected sub-bit line SB 11 , selected bit line selecting transistor BT 11 .

As result, memory cell C 11 crossing points between sub-word line SW 11 sub-bit line SB 11 write data memory cell C 11 .

For reading-out data memory cell, when data stored memory cell C 11 first sub-memory array SMA 1 , for example, intended read out, only main bit line B 1 , for example, selected apply thereto read voltage. Other main bit lines other than main bit line B 1 are not selected. Also, first word line selecting line WSL 1 selected, other word line selecting lines other than first word line selecting line WSL 1 are not selected.

The read current caused flow selected main bit line B 1 memory cell C 11 sub-word line SW 11 through sub-bit line SB 11 . The read current then supplied sense amplifier SA 1 through read transistor RT 11 sense line SL 1 .

At time when data intended written memory cell, current several milliamperes caused flow through corresponding one word line selecting transistors WT 11 WT 1 m, WT 21 WT 2 m WT 3 g WT 3 k. Then, for this current, channel current normal MOS transistor not utilized, but current which caused flow drain, i.e., terminal connected corresponding one sub-word lines SW 11 SW 1 m, SW 21 SW 2 m, SW 3 g SW 3 k substrate utilized.

FIG. 5 schematic block diagram MRAM according third embodiment present invention which plurality sub-memory cell arrays each shown FIG. 4 are arranged.

In figure, sub-memory cell arrays SMA 1 SMA 4 are arranged matrix.

An X decoder/write circuit X 1 arranged left end sub-memory cell array SMA 1 . The X decoder/write circuit X 1 serves drive main word lines W 1 Wm connected common sub-memory cell arrays SMA 1 SMA 2 basis X address XADD. An X decoder/write circuit X 2 arranged left end sub-memory cell array SMA 3 . The X decoder/write circuit X 2 serves drive main word lines Wg Wk connected common sub-memory cell arrays SMA 3 SMA 4 basis X address XADD.

A Y decoder/write circuit Y 1 arranged upper end sub-memory cell array SMA 1 . The Y decoder/write circuit Y 1 serves drive main bit lines B 1 Bn connected common sub-memory cell arrays SMA 1 SMA 3 basis Y address YADD. A Y decoder/write circuit Y 2 arranged upper end sub-memory cell array SMA 2 . The Y decoder/write circuit Y 2 serves drive main bit lines Bh Bj connected common sub-memory cell arrays SMA 2 SMA 4 basis Y address XADD.

A sense amplifier SMA 1 arranged right end sub-memory cell array SMA 2 . A signal read out memory cell sub-memory cell array SMA 1 or sub-memory cell array SMA 2 transferred sense amplifier SMA 1 amplified thereby.

A sense amplifier SMA 2 arranged right end sub-memory cell array SMA 4 . A signal read out memory cell sub-memory cell array SMA 3 or sub-memory cell array SMA 4 transferred sense amplifier SMA 2 amplified thereby.

The write circuit K 1 for sub-memory cell array SMA 1 arranged between sub-memory cell arrays SMA 1 SMA 3 . Output terminals write circuit K 1 are connected sub-bit lines SB 1 SBn, respectively. The write circuit K 1 serves connect each sub-bit lines one power supply line or grounding line basis output signals D 0 E 0 write control circuits 3 4 for receiving write data information.

Write circuits K 2 K 4 are arranged lower end sub-memory cell array SMA 2 , lower end sub-memory cell array SMA 3 lower end memory cell array SMA 4 , respectively. Similarly write circuit K 1 , each these write circuits K 2 K 4 serves connect each sub-bit lines within corresponding sub-memory cell array one power supply line or grounding line basis write data information.

A first BSL driver 1 arranged position corresponding both left end sub-memory cell array SMA 1 upper end X decoder/write circuit X 1 . The bit selecting line BSL 1 for sub-memory cell arrays SMA 1 SMA 2 derived sub-memory cell arrays SMA 1 SMA 2 first BSL driver 1 . At time when bit line selecting line BSL 1 activated, first BSL driver 1 electrically connects main bit line corresponding sub-bit line sub-memory cell array SMA 1 or SMA 2 each other response Y address information.

A second BSL driver 2 arranged position corresponding both left end sub-memory cell array SMA 3 upper end X decoder/write circuit X 2 . The bit line selecting line BSL 2 for sub-memory cell arrays SMA 3 SMA 4 derived sub-memory cell arrays SMA 3 SMA 4 second BSL driver 2 . At time when bit line selecting line BSL 2 activated, second BSL driver 2 electrically connects main bit line corresponding sub-bit line sub-memory cell array SMA 3 or SMA 4 each other response Y address information.

A first WSL/RSL driver 5 circuit for outputting signal WSL 1 accordance with which time when data intended written memory cell, corresponding one sub-word lines sub-memory cell arrays SMA 1 SMA 3 selected, for outputting signal RSL 1 accordance with which time when data intended read out memory cell, corresponding one sub-word lines sub-memory cell arrays SMA 1 SMA 3 selected. A second WSL/RSL driver 6 circuit for outputting signal WSL 2 accordance with which time when data intended written memory cell, corresponding one sub-word lines sub-memory cell arrays SMA 2 SMA 4 selected, for outputting signal RSL 2 accordance with which time when data intended read out memory cell, corresponding one sub-word lines sub-memory cell arrays SMA 2 SMA 4 selected. These WSL/RSL drivers 5 6 are driven basis XADD write/read information.

At time when data intended written memory cell C 11 sub-memory cell array SMA 1 , X decoder/write circuit X 1 , response XADD, selects main word lines W 1 , Y decoder/write circuit Y 1 , response YADD, selects main bit line B 1 . The first BSL driver 1 first WSL/RSL driver 5 , response corresponding address signals, activate bit line selecting signal BSL 1 word line selecting signal WSL 1 , respectively. At this time, word line read selecting signals RSL 1 RSL 2 are not activated. As result, sub-memory cell array SMA 1 having memory cell C 11 belonging thereto selected.

In this embodiment, configuration present invention applied word lines, while conventional configuration applied bit lines. However, conversely, it may also available that configuration present invention applied bit lines, while conventional configuration applied word lines.

Since no channel current used for each current paths word line selecting transistors bit line selecting transistors, but substrate current utilized, large current caused flow with small transistor area irrespective ratio channel width W channel length L. As result, it possible reduce area memory cell array.

FIG. 6 schematic view showing MRAM according fourth embodiment present invention.

The MRAM this embodiment includes: main word line MWL connected X decoder/write circuit; sub-word line SWL connected main word line MWL; word line selecting transistor WT connected sub-word line SWL; main bit line MBL, sub-bit line SBL connected main bit line MBL; TMR memory cell provided between sub-bit line SBL sub-word line SWL. That say, this configuration not substantially different that MRAM shown FIG. 1 least.

In this embodiment, data written memory cell C by utilizing electrostatic capacities Cmw Csw which main word line MWL (corresponding each main word lines W 1 Wm Wg Wk shown FIG. 4) sub-word line SWL (corresponding each sub-word lines SW 11 SW 1 m, SW 21 SW 2 m, SW 3 g SW 3 k shown FIG. 4) have, respectively. First all, X decoder/write circuit previously applies predetermined voltage main word line MWL sub-word line SWL accumulate electric charges (positive electric charges negative electric charges) their electrostatic capacities Cmw Csw, respectively. Then, these accumulated electric charges are assigned Qmw Qsw, respectively. Likewise, X decoder/write circuit previously applies predetermined voltage main bit line MBL (corresponding each main bit lines B 1 Bn Bh Bj shown FIG. 4) sub-bit lines SBL (corresponding each sub-bit lines SB 11 SB 1 n, SB 21 SB 2 n, SB 31 SB 3 n shown FIG. 4) by utilizing electrostatic capacities which main bit line MBL sub-bit line SBL have, respectively, accumulate electric charges their electrostatic capacities, respectively.

Next, predetermined input signal applied signal input gate electrode Vg selecting transistor WT connected sub-word line SWL connected memory cell selected so that selecting transistor WT enters snap back state. At same time, predetermined voltage applied selecting transistor (not shown) connected sub-bit line SBL connected memory cell C selected predetermined timing. As result, electric charges accumulated main word line MBL, sub-word line SWL, main bit line MBL, sub-bit line SBL, respectively, are discharged all once form discharge currents (only discharge current Ic sub-word line SWL illustrated FIG. 6) through selecting transistors. Then, magnetic fields induced by these discharge currents are generated realize magnetic field inversion memory cell C thereby write data memory cell C.

It preferable that order that memory cells crossing points between one selected line unselected lines may prevented being broken down while data written memory cell C through above-mentioned two selecting lines, structure selecting transistor WT optimized so that snap back caused with drain voltage about 1 V for example. By adopting this method, withstanding voltage TMR element depending thickness tunnel film maintained nearly present withstanding voltage (about 1.5 V).

More specifically, snap back drain withstanding voltage selecting transistor WT shown FIG. 6 set about 1 V. The main word line MWL/the sub-word line SWL, main bit line MBL/the sub-bit line SBL memory cell C which data intended written are previously precharged with electricity corresponding about 1 V. Other main word lines/other sub-word lines, other main bit lines/other sub-bit lines are grounded, or voltage about 0.5 V applied thereto.

A voltage required cause snap back phenomenon occur applied word selecting line predetermined voltage applied bit selecting line accordance with signal representing start write operation. Thus, selecting transistor WT put into snap back state cause selecting transistor BT conduct thereby discharge electric charges accumulated through precharging process once form discharge current. Thus, data written memory cell C with this discharge current.

According this embodiment, since data written memory cell with discharge current form which temporarily charged electric charges are instantaneously discharged, there no need use constant current source. Thus, there offered effect that when causing steady write current, e.g., write current first embodiment flow, write current reduced compared with method writing data by utilizing write current supplied constant current source.

While this embodiment, description been given with respect case where write current caused flow corresponding one main word lines corresponding one sub-word lines, write current may also caused flow corresponding one main bit lines corresponding one sub-bit lines.

It should noted that present invention not intended limited above-mentioned embodiments hence various changes modifications thereof may made by those skilled art without changing subject matter invention.

As set forth hereinabove, according present invention, it possible reduce area.