Three-terminal magnetostatically coupled spin transfer-based MRAM cell

We claim:




1. A magnetic memory device, comprising: least three terminals including first, second, third terminals; spin transfer (ST) driven element including first free layer, ST driven element disposed between first terminal second terminal; readout element including second free layer, readout element disposed between second terminal third terminal, wherein magnetization direction second free layer readout element indicates data state, wherein magnetization reversal first free layer within ST driven element magnetostatically causes magnetization reversal second free layer readout element, thereby recording data state.


2. A magnetic memory device defined claim 1, wherein ST driven element includes spin valve (SV).


3. A magnetic memory device defined claim 2, wherein SV current perpendicular plane (CPP) spin valve.


4. A magnetic memory device defined claim 2, wherein spin valve comprises: anti-ferromagnetic (AFM) layer; pinned layer; conductor layer; first free layer.


5. A magnetic memory device defined claim 4, wherein pinned layer synthetic includes: first pinned sub-layer; second pinned sub-layer; Ru layer sandwiched between first second pinned sub-layers, wherein Ru layer promotes anti-ferromagnetic exchange coupling between first second pinned sub-layers.


6. A magnetic memory device defined claim 1, wherein ST driven element includes dual spin valve.


7. A magnetic memory device defined claim 6, wherein dual spin valve comprises: first anti-ferromagnetic (AFM) layer; first pinned layer; first conductor layer; first free layer; second conductor layer; second pinned layer; second anti-ferromagnetic (AFM) layer.


8. A magnetic memory device defined claim 7, wherein second pinned layer synthetic includes: first pinned sub-layer; second pinned sub-layer; Ru layer sandwiched between first second pinned sub-layers, wherein Ru layer sandwiched between first second pinned sub-layers, wherein Ru layer promotes anti-ferromagnetic exchange coupling between first second pinned sub-layers.


9. A magnetic memory device defined claim 1, wherein readout element includes magnetic tunnel junction (MTJ).


10. A magnetic memory device defined claim 9, wherein MTJ comprises: anti-ferromagnetic (AFM) layer; pinned layer; insulating barrier layer; second free layer.


11. A magnetic memory device defined claim 1, wherein readout element includes dual magnetic tunnel junction (MTJ).


12. A magnetic memory device defined claim 11, wherein dual MTJ comprises: first anti-ferromagnetic (AFM) layer; first pinned layer; first insulating barrier layer; second free layer; second insulating barrier layer; second pinned layer; second anti-ferromagnetic (AFM) layer.


13. A magnetic memory device defined claim 1, wherein readout element includes magnetic tunnel junction (MTJ)/spin valve (SV) combination.


14. A magnetic memory device defined claim 13, wherein MTJ/SV combination comprises: first anti-ferromagnetic (AFM) layer; first pinned layer; insulating barrier layer; second free layer; conductor layer; second pinned layer; second anti-ferromagnetic (AFM) layer.


15. A magnetic memory device defined claim 14, wherein second pinned layer synthetic includes: first pinned sub-layer; second pinned sub-layer; Ru layer sandwiched between first second pinned sub-layers, wherein Ru layer promotes anti-ferromagnetic exchange coupling between first second pinned sub-layers.


16. An array magnetic memory devices for reading writing data states, comprising: plurality word lines; plurality bit lines; plurality magnetic memory elements, each magnetic memory element comprising: least three terminals including first, second, third terminals; spin transfer (ST) driven element including first free layer, ST driven element disposed between first terminal second terminal; readout element including second free layer insulating barrier layer, readout element disposed between second terminal third terminal; least one isolation circuitry configured select desired magnetic memory element within array, isolate insulating barrier layer during write operation, wherein readout element, word line, bit line cooperate enable magnetization direction second free layer readout element indicate data state, wherein ST driven element, word line, bit line cooperate enable magnetization reversal first free layer within ST driven element magnetostatically causing magnetization reversal second free layer readout element thereby recording data state.


17. An array magnetic memory devices defined claim 16, wherein said least one isolation circuitry comprises: first gate, first source, first drain; second transistor having second gate, second source, second drain.


18. An array magnetic memory devices defined claim 17, wherein said least one isolation circuitry said least three terminals are configured such that first terminal coupled bit line, second terminal coupled first drain, third terminal coupled second rain, first second sources are coupled ground line.


19. An array magnetic memory devices defined claim 18, wherein first second transistors are configured such that during write operation, current flows bit line through ST driven element, through first transistor, into ground line, during read operation, current flows bit line through readout element, through ST driven element, through second transistor, into ground line.


20. An array magnetic memory devices defined claim 17, wherein said least one isolation circuitry said least three terminals are configured such that first terminal coupled first drain, second terminal coupled bit line, third terminal coupled second drain, first second sources are coupled ground line.


21. An array magnetic memory devices defined claim 20, wherein first second transistors are configured such that during write operation, current flows bit line through ST driven element, through first transistor, into ground line, during read operation, current flows bit line through readout element, through second transistor, into ground line.


22. A method for reading writing data state fro magnetic memory device, comprising: providing least three terminals including first, second, third terminals; providing spin transfer (ST) driven element including first free layer, ST driven element disposed between first terminal second terminal; providing readout element including second free layer, readout element disposed between second terminal third terminal; reversing magnetization direction first free layer within ST driven element, magnetostatically causing magnetization reversal second free layer readout element record data state; indicating data state by detecting magnetization direction second free layer readout element.


23. A method defined claim 22, wherein reversing magnetization direction includes applying voltage between second terminal first terminal.


24. A method defined claim 22, wherein indicating data state includes applying voltage between third terminal first terminal.


25. A method defined claim 22, wherein indicating data state includes applying voltage between third terminal second terminal.


26. A method for reading writing data states for array magnetic memory elements, comprising: providing plurality word lines; providing plurality bit lines; providing plurality magnetic memory elements, each magnetic memory element comprising: least three terminals including first, second, third terminals; spin transfer (ST) driven element including first free layer, ST driven element disposed between first terminal second terminal; readout element including second free layer insulating barrier layer, readout element disposed between second terminal third terminal; least one isolation circuitry configured select desired magnetic memory element within array, isolate insulating barrier layer during write operation; reversing magnetization direction first free layer within ST driven element, magnetostatically causing magnetization reversal second free layer readout element record data state; indicating data state by detecting magnetization direction for second free layer readout element.


27. A method defined claim 26, wherein said least one isolation circuitry comprises: first transistor having first gate, first source, first drain; second transistor having second gate, second source, second drain.


28. A method defined claim 27, further comprising: configuring said least one isolation circuitry said least three terminals, including: connecting first terminal bit line; connecting second terminal first drain; connecting third terminal second drain; connecting first second sources ground line.


29. A method defined claim 28, further comprising: configuring first second transistors, including: directing current flow bit line through ST driven element, through first transistor, into ground line, write data state; directing current flow bit line through readout element, through ST driven element, through second transistor, into ground line, read data state.


30. A method defined claim 27, further comprising: configuring said least one isolation circuitry said least three terminals, including: coupling first terminal first drain; coupling second terminal bit line; coupling third terminal second drain; coupling first second sources word line.


31. A method defined claim 30, further comprising: configuring first second transistors, including: directing current flow bit line through ST driven element, through first transistor, into ground line, write data state; directing current flow bit line through readout element, through second transistor, into ground line read data state.

BACKGROUND

1. Field

The present invention relates generally magnetic memory systems and, more particularly, method system for providing element that employs spin-transfer effect switching that used magnetic memory, such magnetic random access memory (“MRAM”).

2. Description Related Art

Magnetic memories are often used for storing data. One type memory element currently interest utilizes magneto-resistance magnetic element for storing reading data. FIGS. 1 2 depict conventional magnetic elements 100 200 .

The conventional magnetic element 100 , shown FIG. 1, spin valve (SV) 100 includes conventional anti-ferromagnetic (AFM) layer 110 , conventional pinned layer 108 , conventional spacer layer 106 , which typically conductor, conventional free layer 104 . The conventional pinned layer 108 conventional free layer 104 are ferromagnetic. The conventional spacer layer 106 nonmagnetic. The AFM layer 110 used fix, or pin, magnetization pinned layer 108 particular direction. The magnetization free layer 104 free rotate, typically response external field. Contacts, such bottom contact 112 top lead 102 , coupled magnetic element 100 provide electrical contact magnetic element 100 .

The conventional magnetic element 200 , shown FIG. 2, magnetic tunneling junction (MTJ). Portions MTJ 200 are analogous conventional spin valve 100 . Thus, conventional magnetic element 200 includes anti-ferromagnetic layer 210 , conventional pinned layer 208 , insulating barrier layer 206 , free layer 204 . The conventional barrier layer 206 thin enough for electrons tunnel through conventional MTJ 200 . Contacts, such bottom contact 212 top lead 202 , coupled magnetic element 200 provide electrical contact magnetic element 200 .

Depending upon orientations magnetizations free layer 104 or 204 pinned layer 108 or 208 , respectively, resistance conventional magnetic element 100 or 200 , respectively, changes. When magnetizations free layer 104 pinned layer 108 are parallel, resistance conventional spin valve 100 low. When magnetizations free layer 104 pinned layer 108 are anti-parallel, resistance conventional spin valve 100 high. Similarly, when magnetizations free layer 204 pinned layer 208 are parallel, resistance conventional MTJ 200 low. When magnetizations free layer 204 pinned layer 208 are anti-parallel, resistance conventional MTJ 200 high.

In order sense resistance conventional magnetic element 100 , 200 , current driven through conventional magnetic element 100 , 200 . Current driven through conventional magnetic element 100 one two configurations, current plane (“CIP”) current perpendicular plane (“CPP”). However, for conventional magnetic tunneling junction 200 , current driven CPP configuration. In CIP configuration, current driven parallel layers conventional spin valve 100 . Thus, CIP configuration, current driven left right or right left seen FIG. 1. In CPP configuration, current driven perpendicular layers conventional magnetic element 100 , 200 . Thus, CPP configuration, current driven up or down seen FIG. 1 or FIG. 2. The CPP configuration used MRAM having conventional magnetic tunneling junction 200 memory cell.

Recently, spin transfer effect been proposed switching mechanism for magnetic memory elements. See J. C. Slonczewski, “Current-driven Excitation Magnetic Multilayers,” Journal Magnetism Magnetic Materials , vol. 159, p. L1–L5 (1996). In original spin transfer systems, Co/Cu/Co pseudo-spin valve with current perpendicular plane (CPP), similar that shown FIG. 1 (but without AFM layer 210 ), was used. See L. Berger, “Emission Spin Waves by Magnetic Multilayer Traversed by Current,” Phys. Rev. B , Vol. 54, p. 9353 (1996), F. J. Albert, J. A. Katine R. A. Buhman, “Spin-polarized Current Switching Co Thin Film Nanomagnet,” Appl. Phys. Left ., vol. 77, No. 23, p. 3809–3811 (2000).

However, using such spin transfer system presents two primary challenges. First, current required induce switching high, e.g., order 1 mA or greater. Second, output signal small, such that both total resistance change resistance SV-based spin transfer elements are small, e.g., normally less than 2 Ohms 5%, respectively.

One proposed method increasing output signal use magnetic tunnel junction (MTJ) for spin transfer device, similar that shown FIG. 2. See J. C. Slonczewski, “Current-driven Excitation Magnetic Multilayers,” Journal Magnetism Magnetic Materials , vol. 159, p. L1–L5 (1996). The magnetic tunnel junction exhibit large resistance large signal, e.g., >1000 Ohms >40% dR/R, respectively. However, this approach still cannot decrease high operating current sufficiently.

It should apparent discussion above that there need for device method for providing magnetic memory element that consumes low power such that it used high density memory array. Further, there need provide device method for protecting sensitive layers MTJ relatively high write current. The present invention satisfies this need.

SUMMARY

A magnetic memory device for reading writing data state comprises least three terminals including first, second, third terminals. The magnetic memory device also includes spin transfer (ST) driven element, disposed between first terminal second terminal, readout element, disposed between second terminal third terminal. The ST driven element includes first free layer, readout element includes second free layer. A magnetization direction second free layer readout element indicates data state. A magnetization reversal first free layer within ST driven element magnetostatically causes magnetization reversal second free layer readout element, thereby recording data state. In one embodiment, ST driven element includes spin valve (SV). In another embodiment, readout element includes magnetic tunnel junction (MTJ).

In another aspect, array magnetic memory devices for reading writing data states described. The array magnetic memory devices includes plurality word lines, plurality bit lines, plurality magnetic memory elements. Each magnetic memory element includes least first, second, third terminals; spin transfer (ST) driven element, disposed between first terminal second terminal; readout element, disposed between second terminal third terminal; least one isolation circuitry configured select desired magnetic memory element within array. The spin transfer (ST) driven element includes first free layer. The readout element includes second free layer insulating barrier layer. The readout element, word line, bit line cooperate enable magnetization direction second free layer readout element indicate data state. The ST driven element, word line, bit line cooperate enable magnetization reversal first free layer within ST driven element magnetostatically causing magnetization reversal second free layer readout element thereby recording data state. The isolation circuitry also used isolate insulating barrier layer during write operation.

In another aspect, method for reading writing data state for magnetic memory device described. The method includes providing least first, second, third terminals; providing spin transfer (ST) driven element, disposed between first terminal second terminal; providing readout element disposed between second terminal third terminal. The method also includes reversing magnetization direction first free layer within ST driven element, magnetostatically causing magnetization reversal second free layer readout element record data state. The data state indicated by detecting magnetization direction second free layer readout element.

Other features advantages present invention should apparent following description preferred embodiment, which illustrates, by way example, principles invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates conventional magnetic element configured spin valve.

FIG. 2 illustrates conventional magnetic element configured magnetic tunnel junction.

FIG. 3 illustrates magnetic element configured spin valve/magnetic tunnel junction combination.

FIG. 4 illustrates particular embodiment magnetic element illustrated FIG. 3.

FIG. 5 illustrates another particular embodiment magnetic element illustrated FIG. 3.

FIG. 6 illustrates magnetic memory device with lead architecture that includes least three electrical contacts or terminals.

FIG. 7 shows embodiment ST driven element configured spin valve.

FIG. 8 shows another embodiment ST driven element configured dual spin valve.

FIG. 9 shows embodiment readout element configured magnetic tunnel junction (MTJ).

FIG. 10 shows another embodiment readout element configured dual magnetic tunnel junction (MTJ).

FIG. 11 shows another embodiment readout element configured dual magnetic tunnel junction (MTJ)/spin valve (SV) combination.

FIG. 12 illustrates 3-terminal device structure cell using two transistors per cell for isolation selection, accordance with embodiment present invention.

FIG. 13 illustrates 3-terminal device structure cell using two transistors per cell for isolation selection, accordance with another embodiment present invention.

FIG. 14 illustrates embodiment shown FIG. 13 structural layout.

FIG. 15 illustrates 3-terminal device structure cell using two transistors per cell for isolation selection, accordance with another embodiment present invention.

FIG. 16 illustrates 3-terminal device structure cell using two transistors per cell for isolation selection, accordance with another embodiment present invention.

DETAILED DESCRIPTION

To overcome difficulties two approaches addressed FIG. 1 FIG. 2, another approach proposed substantially simultaneously increase output signal lower operating current magnetic element by placing spin transfer element series with magnetic tunnel junction (MTJ). One example approach shown FIG. 3, which magnetic element 300 includes spin transfer driven element (e.g., spin valve) 304 coupled readout element, such magnetic tunnel junction (MTJ) element 308 , through separation layer 306 . Contacts, such bottom contact 310 top lead 302 , coupled magnetic element 300 provide electrical contact magnetic element 300 . Other layers used provide desired structure properties, such seed layer capping layer, are not depicted for clarity.

In magnetic element 300 FIG. 3, current causes magnetization reversal free layer within spin transfer element 304 . In turn, magnetic field this free layer couples magnetostatically with free layer within magnetic tunnel junction (MTJ) readout element 308 . The free layer MTJ readout element 308 responds this field undergoes magnetization reversal. For such approach shown FIG. 3, free layer spin transfer element 304 , which responds spin transfer torque, optimized for low switching current while free layer MTJ readout element 308 optimized for high magnetoresistance.

FIG. 4 illustrates particular embodiment magnetic element 400 , which substantially similar magnetic element 300 shown FIG. 3. The illustrated magnetic element 400 includes spin transfer driven element portion (SV) 402 magnetic tunnel junction element portion (MTJ) 422 . The spin transfer driven element portion 402 comprises anti-ferromagnetic (AFM) layer 404 , pinned layer 406 , spacer conductor layer 408 , free layer 410 . The magnetic tunnel junction element portion 422 comprises anti-ferromagnetic layer 420 , pinned layers 414 , 418 , which sandwich Ruthenium (Ru) layer 416 , insulating barrier layer 412 , free layer 410 . The Ru layer 416 , certain thickness, e.g., between about 5 9 Angstroms, promotes anti-ferromagnetic exchange coupling between two adjacent ferromagnetic films 414 , 418 . The combination three layers 414 , 418 , 416 form “synthetic” pinned layer where non-magnetic layer 416 promotes anti-ferromagnetic exchange coupling between ferromagnetic pinned layers 414 418 . Although particular embodiment FIG. 4 uses Ru layer, other equivalent materials used instead. Thus, it seen that magnetic element 400 shares free magnetic layer 410 between spin transfer driven element portion 402 magnetic tunnel junction element portion 422 .

Since free layer 410 experiences torques pointing same directions both spin transfer driven element 402 magnetic tunnel junction element 422 , spin transfer switching current magnetic element 400 lower than spin transfer switching current magnetic element 100 case shown FIG. 1. Therefore, illustrated embodiment FIG. 4, relatively modest current switch magnetization free layer 410 , where output signal dominated by magnetic tunnel junction element portion 422 .

FIG. 5 illustrates another particular embodiment magnetic element 500 , which substantially similar magnetic element 300 shown FIG. 3. In this embodiment, more than one free layer used combination spin valve/magnetic tunnel junction (MTJ) system, where free layer(s) MTJ element 530 are magnetostatically coupled free layer(s) spin valve (SV) element 502 .

In FIG. 5 illustrated embodiment, SV element 502 comprises anti-ferromagnetic layer 504 , synthetic pinned layer that includes ferromagnetic layers 506 510 sandwiching Ru layer 508 , conducting spacer layer 512 , free layer (I) 514 . The MTJ element 530 comprises anti-ferromagnetic layer 528 , synthetic pinned layer including layers 522 , 526 , which sandwich Ru layer 524 , insulating barrier layer 520 , which thin enough allow electrons tunnel through, free layer (H) 518 . Thus, free layer (I) 514 SV element 502 magnetostatically coupled free layer (H) 518 MTJ element. The SV element 502 MTJ element 530 magnetic element 500 are coupled together with separation layer 516 .

Although placing spin transfer element (e.g., 304 FIG. 3; 402 FIG. 4; 502 FIG. 5) series with MTJ element (e.g., 308 FIG. 3; 422 FIG. 4; 530 FIG. 5) increase output signal lower operating current, this mode operation also presents limitation. For example, configuration shown FIG. 5, write current read current must flow through both spin transfer element 502 MTJ element 530 . Thus, write current that switches free layer 514 within spin transfer element 502 must small enough so that it does not damage insulating barrier layer 520 MTJ element 530 .

If current (induced by applied voltage) applied MTJ element 530 too large, applied current cause insulating barrier layer 520 within MTJ element 530 undergo breakdown, such that insulating properties insulating barrier layer 520 are destroyed. The cause this breakdown due dielectric breakdown, energetic growth existing pinholes, or both. Therefore, operational voltage fundamentally constrained below this breakdown voltage, V b , thus limit operational current flowing through MTJ element 530 . Furthermore, for long-term reliability these magnetic tunnel junctions, maximum operating voltage constrained even less than V b .

To prevent destruction tunnel junction during write operation, resistance area product, RA, subject following criteria: RA<V b /J st , where J st current density which spin transfer causes magnetization reversal. Thus, using typical values J st equal about 0.2 A/μm 2 V b equal about 0.3 V for low resistance barriers, resistance area product RA required less than 1.5 Ω-μm 2 . Those who are skilled art low resistance MTJ barrier low RA barriers, know that this difficult accomplish manufacturable environment. Also due limitations current low RA barriers, dR/R most likely low, less than 15%. Furthermore, resistance device manufacturable with near term lithography limitations dictates that resistance would also low, less than 200 Ω. This would smaller than selection transistor resistance, thus increasing read access time. However, spin transfer switching current reduced these issues become lessened because higher resistance MTJ insulating barriers could used.

Finally, even if switching current reduced such that device could reliably switched with spin transfer current without destroying MTJ barrier, there still another problem. In order ensure that read current does not also write device, read current preferably constrained some small fraction write current. For example, resistance MTJ barrier approximately 5 kΩ write voltage 0.5 V produces write current 0.1 mA. Although ratio read current write current depend write current distributions, assume for this example that read current constrained three times smaller than write current. Constraining read current I r <(I w /3) results I r being approximately 0.033 mA. This then constrains V r approximately 0.5V/3, which results approximately 166 mV. Assuming dR/R about 30%, read signal produces only about 50 mV. Using single MTJ element, this signal could only increased by narrowing read-write margins or increasing breakdown voltage barrier material.

To obviate above-described difficulties, spin transfer driven magnetostatically coupled concept adapted, such that MTJ element spin transfer element are separated with lead architecture. In this lead architecture, addition top electrical contact bottom electrical contact, middle electrical contact provided between MTJ element spin transfer element.

FIG. 6 illustrates magnetic memory device 600 with above-described lead architecture accordance with embodiment present invention. The illustrated magnetic memory device 600 , which reads writes data state, includes least three electrical contacts or terminals, including top lead 602 , middle contact 606 , bottom contact 610 . The magnetic memory device 600 also includes spin transfer (ST) driven element 604 disposed between top lead 602 middle contact 606 , readout element 608 disposed between middle contact 606 bottom contact 610 . In illustrated embodiment FIG. 6, ST driven element 604 configured spin valve, while readout element 608 configured magnetic tunnel junction (MTJ).

The ST driven element 604 includes first free layer 612 , while readout element includes second free layer 614 . The spin torque applied current causes magnetization reversal first free layer 612 within ST driven element 604 . In turn, magnetic field first free layer 612 couples magnetostatically with second free layer 614 within MTJ readout element 608 . The second free layer 614 MTJ readout element 608 responds this field undergoes magnetization reversal, thus changing state data. Therefore, during operation magnetic memory device 600 , write operation utilize ST driven element 604 store data state by enabling first free layer 612 magnetostatically interact with second free layer 614 . A read operation involves indicating data state by detecting magnetization direction second free layer readout element 608 . With this arrangement, suitable logic drive circuitry, current forced travel through ST driven element 604 , readout element 608 , or both.

FIG. 7 FIG. 8 illustrate two embodiments ST driven element 604 shown FIG. 6. FIG. 7 shows embodiment ST driven element configured spin valve 700 , which includes anti-ferromagnetic (AFM) layer 702 , synthetic pinned layer that includes ferromagnetic layers 704 708 sandwiching Ru layer 706 , spacer conductor layer 710 , free layer (I) 712 . FIG. 8 shows another embodiment ST driven element configured dual spin valve 800 for lower switching current. The dual spin valve 800 includes first anti-ferromagnetic (AFM) layer 802 , first second pinned layers 804 , 808 , which sandwich Ru layer pressed material 806 , first spacer conductor layer 810 , free layer (I) 812 . The dual spin valve 800 further includes second spacer conductor layer 814 , third pinned layer 816 , second AFM layer 818 .

FIGS. 9 through 11 illustrate various embodiments readout element 608 shown FIG. 6. FIG. 9 shows embodiment readout element configured magnetic tunnel junction (MTJ) 900 , which includes anti-ferromagnetic (AFM) layer 902 , synthetic pinned layer that includes ferromagnetic layers 904 908 sandwiching Ru layer 906 , insulating barrier layer 910 , free layer (H) 912 .

FIG. 10 shows another embodiment readout element configured dual MTJ 1000 for higher signal. The dual MTJ 1000 includes first AFM layer 1002 , synthetic pinned layer that includes first second ferromagnetic layers 1004 1008 sandwiching Ru layer 1006 , first insulating barrier layer 1010 , free layer (H) 1012 . The dual MTJ 1000 further includes second insulating layer 1014 , synthetic pinned layer that includes third fourth ferromagnetic layers 1016 1020 sandwiching Ru layer 1018 , second AFM layer 1022 .

FIG. 11 shows another embodiment readout element configured dual magnetic tunnel junction (MTJ)/spin valve (SV) combination 1100 for lower switching current. The dual MTJ/SV combination 1100 includes first AFM layer 1102 , synthetic pinned layer that includes first second ferromagnetic layers 1104 1108 sandwiching Ru layer 1106 , insulating barrier layer 1110 , free layer 1112 . The dual MTJ/SV combination 1100 further includes spacer conductor layer 1114 , third pinned layer 1116 , second AFM layer 1118 .

Referring back FIG. 6, configuration magnetic memory device 600 , such that write current forced follow different path than read current, allows satisfactory resolution issues with breakdown voltage low read signal. For example, write current forced through ST driven element 604 via middle contact 606 into top contact 602 , circumventing MTJ element 608 . Thus, large write current does not flow through MTJ readout element 608 therefore cannot cause damage sensitive insulating barrier layer MTJ readout element 608 . Furthermore, maximum voltage that long-term reliability allows applied MTJ readout element 608 for read operation.

A suitable selection circuitry employed such that read current does not flow through ST driven element 604 prevent possibility accidental writing during read operation. Alternatively, read current flow through both ST driven element 604 MTJ readout element 608 . In latter case, resistance MTJ readout element 608 must carefully chosen such that read current does not cause spin transfer driven magnetization reversal free layer ST driven element 604 . In such case, read current must constrained be

I read <(I write /x), [1]

where x some scaling factor that depends write distributions. Since

I read ˜V read /R MTJ , [2]

combining Equations [1] [2]:

R MTJ >(V read *x)/I write [3]

Applying some reasonable values V read ˜0.2 V, I write ˜0.2 mA, x˜ 3 , into Equation [3] yields R MTJ greater than 3 kΩ, which reasonable value resistance MTJ element.

Referring FIG. 6 again, isolation circuitry required select single element, such magnetic memory device 600 , within dense array magnetic elements. FIGS. 12 through 16 represent four different embodiments configured provide this selection dense array.

In first illustrated embodiment FIG. 12, 3-terminal device structure cell 1200 uses two transistors 1230 , 1232 per cell for isolation selection. One transistor 1230 connected spin transfer element (i.e., spin valve) 1204 through middle contact 1206 while another transistor 1232 connected MTJ readout element 1208 through bottom contact 1220 .

A write operation includes sending current pulse through bridging middle contact 1206 , then through spin transfer element 1204 . This achieved by applying voltage along Word Line (WL) 1210 another voltage along Bit Line (BL) 1202 . The transistor source 1216 grounded via Ground Line (GL) 1212 .

A read operation includes sending current pulse through MTJ element 1208 then through spin transfer element 1204 . This achieved by applying voltage along WL 1214 another voltage along BL 1202 . The transistor source 1218 grounded via GL 1212 . As read current flows through both MTJ readout element 1208 spin transfer element 1204 , resistance MTJ readout element 1208 must carefully chosen such that read current does not also write device 1200 .

The second embodiment, illustrated FIG. 13 FIG. 14, refinement first embodiment. The memory cell 1300 includes two transistors 1320 , 1322 that share common source 1314 for isolation. For example, two transistor series would include drain/gate/shared source/gate/drain instead drain/gate/source/isolation/source/gate/drain. The transistor 1320 connected spin transfer element (i.e., spin valve) 1304 through middle contact 1306 , while transistor 1322 connected MTJ readout element 1308 through bottom contact 1318 . The BL 1302 connected top contact 1301 . The shared source 1314 connected GL 1312 .

FIG. 14 illustrates second embodiment structural layout with like numbers designating like elements FIG. 13. Thus, write operation includes sending current pulse through bridging contact 1309 , through middle contact 1306 , then through spin transfer element 1304 . This achieved by applying voltage along WL 1310 well voltage BL 1302 , while grounding GL 1312 shared transistor source 1314 .

A read operation includes sending current pulse through MTJ element 1308 then through spin transfer element 1304 . This achieved by applying voltage along WL 316 well voltage BL 1302 , while grounding GL 1312 . As read current flows through both MTJ readout element 1308 spin transfer element 1304 , resistance MTJ readout element 1308 must carefully chosen such that read current does not also write device 1300 .

A third embodiment, illustrated FIG. 15, uses two transistors 1520 , 1522 per cell 1500 for isolation selection. However, middle contact line 1505 used bit line BL 1506 . In this configuration, write current directed solely through spin transfer element 1504 , read current directed solely through MTJ readout element 1508 . Thus, resistance MTJ element 1508 does not need tailored such that read current limited smaller than write current.

A write operation includes sending current pulse through bit line 1506 , through transistor 1520 connected directly spin transfer element 1504 , through spin transfer element 1504 , then out ground line GL 1506 . This achieved by applying voltage along gate WL 1510 transistor 1520 well voltage BL 1506 , while grounding GL 1512 . A read operation includes sending current pulse through MTJ element 1508 . This achieved by applying voltage along BL 1506 well voltage WL 1514 , while grounding GL 1512 .

Finally, fourth embodiment, illustrated FIG. 16, refinement third embodiment. In fourth embodiment, two transistors 1520 , 1522 third embodiment share common source 1602 . For example, two transistor series 1520 , 1522 would include drain/gate/shared source/gate/drain instead drain/gate/source/isolation/source/gate/drain. The shared source 1602 connected single ground line GL 1512 .

The present invention been described above terms exemplary embodiments so that understanding present invention conveyed. Any embodiment described herein “exemplary” not necessarily construed preferred or advantageous over other embodiments. Moreover, there are configurations for magnetic memory device associated components or elements not specifically described herein but with which present invention applicable. The present invention should therefore not seen limited particular embodiments described herein, but rather, it should understood that present invention wide applicability with respect magnetic memory device generally. All modifications, variations, or equivalent arrangements implementations that are within scope attached claims should therefore considered within scope invention.