Test terminal negation circuit for protecting data integrity

What claimed is:




1. A test terminal negation circuit comprising: switch circuit which receives test signal one or more test terminals outputs it asserted state it or predetermined negated state test object circuit; test signal control circuit which controls output signal switch circuit asserted state or negated state; test mode signal generation circuit which generates test mode signal which asserts output signal switch circuit outputs it test signal control circuit time test mode; negating signal generation circuit which output negating signal for forcing output signal switch circuit into negated state test signal control circuit comprises electrically rewritable nonvolatile memory element, wherein when negating signal outputted negating signal generation circuit, test signal control circuit negates output signal switch circuit even when test mode signal outputted test mode signal generation circuit.


2. The test terminal negation circuit according claim 1, wherein negating signal generation circuit comprises first nonvolatile memory element second nonvolatile memory element which MOSFET structure, first inverter circuit second inverter circuit, sources first nonvolatile memory element second nonvolatile memory element are connected ground voltage, gates first nonvolatile memory element second nonvolatile memory element are connected power supply voltage, drain first nonvolatile memory element connected input first inverter circuit output second inverter circuit, drain second nonvolatile memory element connected output first inverter circuit input second inverter circuit, output either first inverter circuit or second inverter circuit output negating signal generation circuit.


3. The test terminal negation circuit according claim 2, wherein output level negating signal generation circuit varied by threshold voltage difference between first nonvolatile memory element second nonvolatile memory element.


4. A method negating test signal comprising: step using test terminal negation circuit according claim 1, step outputting negating signal by performing electrical rewriting nonvolatile memory element negating signal generation circuit after test completed.


5. A method negating test signal comprising: step using test terminal negation circuit according claim 2; step outputting negating signal by performing electrical rewriting either first nonvolatile memory element or second nonvolatile memory element negating signal generation circuit after test completed.


6. A nonvolatile semiconductor memory device comprising test terminal negation circuit according claim 1.


7. An IC card comprising nonvolatile semiconductor memory device according claim 6.

CROSS REFERENCE TO RELATED APPLICATTION

This Nonprovisional application claims priority under 35 U.S.C. §119(a) Patent Application No. 2004-094572 filed Japan Mar. 29, 2004, entire contents which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field Invention

The present invention relates test terminal negation circuit which test signal test terminal not received using nonvolatile memory after test completed.

2. Description Related Art

Recently, IC card which nonvolatile memory mounted been focus attention. Although terminal IC card standardized ISO7816, there are various kinds test terminals facilitate test. In normal operation, since data exchanged by authenticating reader/writer like encrypting data, secret data not leaked.

As conventional technique, there method outputting test signal test terminal test object circuit by activating output test mode signal generation circuit turn switch circuit when test terminal used, circuit constitution method shown FIG. 3 (refer Japanese Unexamined Patent Publication No. 2002-269523, for example). Referring FIG. 3, each circuit comprises test terminal 301 , switch circuit 302 , nonvolatile memory circuit 303 tested, test mode signal generation circuit 304 . The switch circuit 302 turned when output N 3 test mode signal generation circuit 304 activated, then output N 1 test terminal 301 transmitted output N 2 switch circuit 302 control nonvolatile memory circuit 303 . In addition, switch circuit 302 turned off when output N 3 test mode signal generation circuit 304 inactivated, so that output N 1 test terminal 301 not transmitted output N 2 switch circuit 302 . As result, nonvolatile memory circuit 303 cannot controlled test terminal 301 .

However, when test mode activated falsely by operating test mode signal generation circuit for use other than test, information IC card could easily read out using test terminal.

In addition, although Japanese Unexamined Patent Publication No. 2002-269523 discloses method erasing information stored nonvolatile memory IC card when it detected that test mode activated falsely, it necessary provide additional circuit detect false activation test mode this method.

SUMMARY OF THE INVENTION

The present invention been made view above problems it object present invention prevent test mode being falsely activated test terminal by negating test terminal simple circuit constitution.

A test terminal negation circuit according present invention attain object comprises switch circuit which receives test signal one or more test terminals outputs it asserted state it or predetermined negated state test object circuit, test signal control circuit which controls output signal asserted state or negated state switch circuit, test mode signal generation circuit which generates test mode signal which asserts output signal switch circuit outputs it test signal control circuit time test mode, negating signal generation circuit which output negating signal negate output signal switch circuit by force, test signal control circuit comprises electrically rewritable nonvolatile memory element, which when negating signal outputted negating signal generation circuit, test signal control circuit negates output signal switch circuit even when test mode signal outputted test mode signal generation circuit.

In addition, test terminal negation circuit according present invention characterized that negating signal generation circuit comprises first nonvolatile memory element second nonvolatile memory element which MOSFET structure, first inverter circuit second inverter circuit, which sources first nonvolatile memory element second nonvolatile memory element are connected ground voltage, gates first nonvolatile memory element second nonvolatile memory element are connected power supply voltage, drain first nonvolatile memory element connected input first inverter circuit output second inverter circuit, drain second nonvolatile memory element connected output first inverter circuit input second inverter circuit, output second inverter circuit output negating signal generation circuit.

Furthermore, test terminal negation circuit according present invention characterized that output level negating signal generation circuit varied by threshold voltage difference between first nonvolatile memory element second nonvolatile memory element.

According test terminal negation circuit present invention, once negating signal generation circuit outputs negating signal, since test signal for activating test mode outputted negated state switch circuit, test mode prevented being falsely activated test terminal without detecting false activation.

A method negating test terminal according present invention attain object characterized that negating signal outputted by performing electrical rewriting nonvolatile memory element negating signal generation circuit test terminal negation circuit according present invention after test completed. Especially, when negating signal generation circuit comprises first nonvolatile memory element second nonvolatile memory element having MOSFET structure, first inverter circuit second inverter circuit described above, it preferable that negating signal outputted by performing electrical rewriting either one first nonvolatile memory element or second nonvolatile memory element negating signal generation circuit after test completed.

According test terminal negating method present invention, since negating signal generation circuit outputs negating signal using test terminal negation circuit according present invention after test completed, test mode prevented being activated falsely test terminal, so that data test object circuit prevented being operated by test terminal.

A nonvolatile semiconductor memory device according present invention characterized by comprising test terminal negation circuit having above characteristics. In addition, IC card present invention characterized by comprising nonvolatile semiconductor memory device having above characteristics. Thus, information nonvolatile semiconductor memory device or IC card prevented being read illegally.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 circuit diagram showing embodiment test terminal negation circuit according present invention;

FIG. 2 circuit diagram showing embodiment negating signal generation circuit test terminal negation circuit according present invention;

FIG. 3 diagram showing conventional circuit constitution example transmit test signal test terminal test object circuit effectively time test mode;

FIG. 4 block diagram showing embodiment nonvolatile semiconductor memory device according present invention;

FIG. 5 block diagram showing embodiment IC card according present invention.

DESCRIPTION OF PREFERRED EMBODIMENTS

An embodiment present invention described with reference drawings. FIG. 1 circuit diagram showing embodiment test terminal negation circuit according present invention (referred “the circuit present invention” occasionally hereinafter). As shown FIG. 1, circuit 100 present invention comprises switch circuit 102 , test mode signal generation circuit 103 , negating signal generation circuit 104 , test signal control circuit 105 .

The switch circuit 102 receives test signal test terminal 101 outputs it asserted state it or predetermined negated state, nonvolatile memory circuit 106 which object circuit tested, depending level output node N 1 test signal control circuit 105 . The switch circuit 102 comprises, for example, CMOS transfer gate like.

The test mode signal generation circuit 103 outputs test mode signal which asserts signal outputted output node N 5 switch circuit 102 , output node N 3 test signal control circuit 105 time test mode, so that test signal test terminal 101 outputted nonvolatile memory circuit 106 it asserted state.

The negating signal generation circuit 104 so constituted that it output negating signal which negates signal outputted output node N 5 switch circuit 102 by force, output node N 2 test signal control circuit 105 . More specifically, shown FIG. 2, negating signal generation circuit 104 comprises first nonvolatile memory element 201 second nonvolatile memory element 202 which MOSFET structure, first inverter circuit 203 second inverter circuit 204 . Here, output node first inverter circuit 203 output node N 2 negating signal generation circuit 104 . The first second nonvolatile memory elements 201 202 may same structure that nonvolatile memory element used nonvolatile memory circuit 106 . According example shown FIG. 2, flash memory element having stack type floating gate structure assumed each nonvolatile memory elements 201 202 .

According negating signal generation circuit 104 shown FIG. 2, threshold voltages first second nonvolatile memory elements 201 202 are lower than power supply voltage voltage difference between threshold voltages small initial state when test started. For example, when first second inverter circuits 203 204 are CMOS inverters, case where W/L (gate width/gate length) P-type MOSFET 1.0/9.8 (μm), W/L N-type MOSFET 1.8/0.8 (μm), since gate length P-type MOSFET each inverter circuits 203 204 long current driving ability low state where first second nonvolatile memory elements 201 202 are both ON, outputs inverter circuits 203 204 become ground voltage or close it.

When test completed, writing operation performed second nonvolatile memory element 202 increase its threshold voltage become power supply voltage level or more, for example. As result, difference generated drain currents flowing first nonvolatile memory element 201 second nonvolatile memory element 202 , so that output first inerter circuit 203 becomes high level (for example, power supply voltage level) output second inverter circuit 204 becomes low level (for example, ground voltage level). Thus, voltage levels are maintained by two inverter circuits 203 204 . Therefore, output level negating signal generation circuit 104 transited low level high level by performing writing operation second nonvolatile memory element 202 when test completed, generate threshold voltage difference between first nonvolatile memory element 201 second nonvolatile memory element 202 , then negating signal outputted.

When test started, voltage level output node N 2 negating signal generation circuit 104 low level when test mode signal generation circuit 103 activated test mode signal output output node N 3 , test signal control circuit 105 activated activated signal outputted output node N 1 switch circuit 102 . Then, switch circuit 102 turned transmits test signal outputted output node N 4 test terminal 101 , output node N 5 it asserted state, control nonvolatile memory circuit 106 .

When test completed, described above, by transiting level output node N 2 negating signal generation circuit 104 high level, output signal output node N 1 test signal control circuit 105 inactivated turn off switch circuit 102 regardless output state test mode signal output node N 3 test mode signal generation circuit 103 . As result, test signal outputted output node N 4 test terminal 101 negated predetermined state it not transmitted output node N 5 , so that nonvolatile memory circuit 106 cannot controlled test terminal 101 .

Therefore, although nonvolatile memory circuit 106 controlled by test signal outputted test terminal 101 time test, nonvolatile memory circuit 106 cannot controlled test terminal 101 after test completed.

The circuit constitution negating signal generation circuit 104 not limited that shown FIG. 2 this embodiment. In addition, although one test terminal 101 illustrated FIG. 1, plurality test terminals 101 may provided.

FIG. 4 shows embodiment nonvolatile semiconductor memory device according present invention. As shown FIG. 4, nonvolatile semiconductor memory device 400 according present invention comprises test terminal 401 , test terminal negation circuit 402 according present invention, control circuit 403 , nonvolatile memory 404 . The control circuit 403 receives test signal test terminal 401 carries out predetermined test mode process nonvolatile memory 404 . Since test terminal negation circuit 402 according present invention provided, test signal test terminal 401 negated after test, so that test mode prevented being activated falsely nonvolatile memory 404 prevented being controlled test terminal 401 .

FIG. 5 shows embodiment IC card according present invention. As shown FIG. 5, IC card 500 according present invention comprises test terminal 510 , microcomputer 509 , non-contact interface circuit 507 , contact interface circuit 508 . The microcomputer 509 comprises test terminal 501 , test terminal negation circuit 502 according present invention, CPU 503 , nonvolatile memory 504 , ROM 505 RAM 506 , so that test terminal negation circuit 502 according present invention provided similar nonvolatile semiconductor memory device 400 shown FIG. 4. A test signal inputted test terminal 510 IC card 500 outputted test terminal negation circuit 502 through test terminal 501 microcomputer 509 , test signal outputted nonvolatile memory 504 asserted state or negated state depending internal state test terminal negation circuit 502 . Since test terminal negation circuit 502 according present invention provided, test signal test terminal 510 negated after test, so that test mode prevented being activated falsely nonvolatile memory 504 IC card prevented being controlled test terminal 510 .

According present invention, described above, since signal test terminal negated after test, there provided nonvolatile semiconductor memory device which not leak inside information. Furthermore, IC card provided with above nonvolatile semiconductor memory device IC card with high-security level.

Although present invention been described terms preferred embodiments, it appreciated that various modifications alterations might made by those skilled art without departing spirit scope invention. The invention should therefore measured terms claims which follow.