Non-volatile memory architecture to improve read performance

What claimed is:




1. A memory array, comprising: plurality sectors comprising memory cells, wherein each sector divided into groups memory cells each group memory cells divided into sub-groups memory cells; plurality bit lines coupled memory cells each sub-group; set first multiplexers, each adapted receive bit lines sub-group first sector; set second multiplexers, each adapted receive bit lines sub-group second sector; set first sense amplifiers, each adapted receive output one set first multiplexers one set second multiplexers, wherein outputs first sense amplifiers associated with group memory cells are coupled together; set second sense amplifiers, each adapted receive coupled outputs group first sense amplifiers.


2. The array claim 1, wherein coupled outputs are complementary.


3. The array claim 1, wherein coupling with wired-OR connection.


4. The array claim 1, wherein set first sense amplifiers are located along periphery array.


5. The array claim 1, wherein coupled outputs span height array.


6. The array claim 1, wherein memory cells are nonvolatile memory cells.


7. The array claim 1, wherein number second sense amplifiers equal number groups memory cells sector.


8. The array claim 1, wherein number first sense amplifiers equal number sub-groups sector.


9. The array claim 1, wherein one first or second sectors used reference for set first sense amplifiers.


10. The array claim 9, wherein other first or second sectors contains memory cell read.


11. A method reading memory cell within array memory cells, array comprising plurality sectors memory cells, method comprising: selecting memory cell first one sectors; providing reference signal second one sectors, wherein second one sectors adjacent first one sectors; generating first signal based value selected memory cell reference signal; generating second signal based first signal.


12. The method claim 11, wherein generating first signal comprises sensing with sense amplifiers.


13. The method claim 12, further comprising placing sense amplifiers along periphery portion memory array.


14. The method claim 11, further comprising dividing each sector into groups memory cells dividing each group memory cells into sub-groups memory cells.


15. The method claim 14, further comprising coupling bit line each column memory cells sub-group.


16. The method claim 15, further comprising coupling sense amplifier each memory cells sub-group.


17. The method claim 16, further comprising coupling global sense amplifier sense amplifiers sub-group.


18. The method claim 11, further comprising providing common reference current second one sectors.


19. The method claim 18, further comprising providing common reference current all sectors not containing selected memory cell.


20. The method claim 19, wherein common reference current generated global current source.


21. The method claim 20, further comprising placing global current source along periphery array.


22. The method claim 11, wherein memory cell nonvolatile memory cell.

BACKGROUND

1. Field Invention

The present invention relates generally semiconductor memory devices, more particularly read architectures for non-volatile memories.

2. Related Art

Non-volatile semiconductor memories arrays are widely used store written or programmed information or data. The information or data, represented “1” or “0”, stored individual memory cells, such EEPROMs, EPROMs, NOR-type flash memory cells, or NAND cells. An array such individual memory cells are interconnected by columns bit lines rows word lines. Associated bit-line word-line decoders allow specific memory cells accessed or read, erased, programmed by applying appropriate voltages selected bit lines word lines. In typical read operation, read circuit senses threshold voltage floating gate transistor memory cell determine value or data stored cell. The sensing with conventional sense amplifier that compares voltage or corresponding current memory cell with reference voltage or current. This comparison, known art, allows content stored accessed memory cell read out.

FIG. 1 shows portions conventional memory array 100 , which includes N sectors 102 , with each sector partitioned into M groups 113 L memory cells row. Each column groups 113 shares global bit line 104 , reference global bit line 106 , bit line multiplexer 108 , dummy bit line multiplexer 110 , sense amplifier 112 . Within each sector, there are M*L sub-bit lines 114 M reference sub-bit lines 107 . Many elements are not shown for clarity, such memory cells within each sector 102 , word lines along x-direction, word line bit line decoders. Note also that dummy bit line multiplexers 110 are typically located away bit line multiplexers 108 , discussed below. Within each sector, memory cells are arranged rows columns, with each group 113 L memory cells along row having L global bit lines 104 one reference global bit line 106 .

For example, for array having K=4096 memory cells across memory cells within each sector partitioned groups L=512 memory cells, there are M=K/L=8 reference global bit lines 106 . Each partitioned group 113 within sector also associated with one bit line multiplexer 108 , one dummy bit line multiplexer 110 , one sense amplifier 112 . The bit-line multiplexers are L:1 multiplexers, dummy bit line multiplexers are similar structure bit line multiplexers, discussed below. The output signal bit line multiplexer (representing value stored selected memory cell) output signal dummy bit line multiplexer (representing reference signal) are input sense amplifier. The sense amplifier compares two input signals generates signal representing data stored selected memory cell.

Each row memory cells sector 102 associated with one word line. Each column memory cells sector 102 associated with one sub-bit line 114 that spans only height sector, where sub-bit line connected source (or drain) each memory cell column. One global bit line 104 that spans entire height N sectors 102 coupled each N sub-bit lines 114 along column array by switch or select transistor (not shown). When desired memory cell read, appropriate voltages are applied corresponding word line select line, which charges or discharges attached sub-bit line depending type memory cell data stored cell. The sub-bit line associated with selected memory cell electrically coupled its corresponding global bit line via switch or select transistor. This global bit line then selected by L:1 bit line multiplexer for use by sense amplifier. During read operation, only one sector being selected time. Sub-bit lines unselected sectors are electrically isolated main bit line with their select transistors being turned off. Such arrangement scheme known commonly referred divided bit line scheme or architecture.

Divided bit line schemes are used improve read performance or reduce read times, which become increasingly long with ever-increasing array sizes. During read operation, selected bit-line charged or discharged by cell current pre-defined level, known art. The time needed charge or discharge proportional total parasitic capacitance associated with bit-line. Thus, memory arrays become larger, bit-lines become longer bit line multiplexers become wider, resulting larger parasitic capacitances. This turn increases signal development time.

The value total capacitance that charged or discharged by cell current during read operation expressed follows:

C total =C DL +C BLM +C GBL +C SBL (1)

where C total total capacitance, C DL data line capacitance, C BLM bit line multiplexer capacitance, C GBL global bit line capacitance, C SBL sub-bit line capacitance. Both C DL C BLM are proportional width bit line multiplexer. C SBL linearly proportional length sub-bit line or number cells sub-bit line. Thus, by dividing bit lines into smaller sub-bit lines, total bit-line capacitance reduced read times are improved. The signal development time for read operation given follows:
t SD , total = C total · Δ ⁢ ⁢ V I cell = C DL · Δ ⁢ ⁢ V I cell + C BLM · Δ ⁢ ⁢ V I cell + C GBL · Δ ⁢ ⁢ V I cell + C SBL · Δ ⁢ ⁢ V I cell = t SD , DL + t SD , BLM + t SD , GBL + t SD , SBL , ( 2 )

where ΔV change signal level needed developed for sense amplifier produce correct output corresponding stored data selected memory cell, I cell cell current, t SD,DL time it takes I cell develop ΔV data line, t SD,BLM time it takes I cell develop ΔV capacitance associated with bit line multiplexer, t SD,GBL time it takes I cell develop ΔV global bit line, t SD,SBL time it takes I cell develop ΔV sub-bit line. As C SBL decreases, C total decreases (see equation (1)), which decreases total signal development time t SD,total (see equation (2)).

However, minimal feature size semiconductor manufacturing process continues shrink, dimensions memory cell become smaller, memory higher density becomes achievable desirable. Higher density results larger array size turn larger parasitic capacitances. At same time, smaller memory cells usually result smaller cell currents charge or discharge such capacitances. Both larger capacitance smaller cell current contribute increase sense time.

Another disadvantage with such divided bit line scheme that mismatch capacitance loading between regular bit line reference bit line. In order accurately sense value selected memory cell, capacitance associated with dummy bit line multiplexer (element 110 FIG. 1) should closely matched capacitance bit line multiplexer (element 108 FIG. 1) carrying signal selected memory cell possible. To that objective, dummy bit line multiplexer similar structure bit line multiplexer. For example, if bit line multiplexer 16:1 MUX, bit line multiplexer formed with 16 transistors, each having one terminal connected global bit line, one terminal commonly connected together MUX output, gate coupled select signal for selecting desired bit line for output. The dummy bit line multiplexer would then also 16 transistors, with one transistor connected reference bit line remaining 15 transistors turned off. This structure then similar capacitance regular bit line multiplexer.

However, because space restrictions, dummy bit line multiplexer 110 cannot placed adjacent or near bit line multiplexer 108 shown FIG. 1. In practical layout, dummy bit line multiplexer located along periphery array. As such, signals traveling through dummy bit line multiplexer must propagate through longer transmission lines reach sense amplifier. Consequently, mismatch capacitance loading between dummy bit line multiplexer regular bit line multiplexer increased. This mismatch reduces read performance array by increasing read time maintain same level accuracy. Building reference bit line reference bit line multiplexer with identical layout parasitic capacitances those regular bit line bit line multiplexer very costly and/or greatly increases array size extent that such option not practical.

Accordingly, there need for improved read architecture method for nonvolatile memory arrays that overcomes disadvantages conventional read architectures, such described above.

SUMMARY

The present invention provides memory array with read circuitry for improved read performance. In one embodiment, memory array divided into even number sectors, where each sector further divided into groups memory cells groups divided into sub-groups. Thus, each sub-group contains array memory cells, which may nonvolatile, flash EPROM, EEPROM, among others. Each pair sectors shares same read circuitry, which includes multiplexers connected bit lines local sense amplifiers receiving output multiplexers.

Each sub-group contains L columns memory cells L bit lines connected corresponding one L memory cells. An L:1 multiplexer associated with each sub-group select one L bit lines its output. A corresponding L:1 bit line multiplexer opposite sector. The output each two multiplexers input local sense amplifier that generates “true” output corresponding sensed value “complement” output signal. The local sense amplifier senses data selected cell amplifies difference signal for “first stage” sensing. Thus, each sub-group memory cells associated with one multiplexer shares one local sense amplifier with multiplexer corresponding sub-group opposite sector.

Each group within sector contains M sub-groups, with each group sharing global sense amplifier with group corresponding opposite sector. Each group includes M local sense amplifiers, where “true” output sense amplifiers are commonly connected, such by wired-OR connection. Similarly, “complement” output sense amplifiers are commonly connected, again such with wired-OR connection. This wired-OR connection forms data line DL its complement {overscore (DL)}. DL {overscore (DL)} are input global sense amplifier that amplifies sense signal local sense amplifiers provide “second stage” sensing. Thus, each paired group memory cells associated with one global sense amplifier, M local sense amplifiers, 2M L:1 multiplexers.

The total sense time needed for read operation sum time for sensing current charge or discharge associated bit lines (local sense amplifiers) time for sensing current charge or discharge data line (global sense amplifiers). The total sense time reduced, according present invention, by increasing sensing current for global sense amplifiers. This accomplished by increasing size local sense amplifiers, which may lie along periphery device. Further, groups sub-groups may divided into larger or smaller groups change granularity memory array. Finer granularity first stage sense amplifier makes it possible use bit line multiplexers narrower width which turn allows simpler single stage multiplexer design with smaller parasitic capacitance.

The present invention also provides better matching bit line loading. In read operation, bit line opposite sector same column location used reference bit line. The opposite sector not enabled for read operation. The reference bit line selected by corresponding multiplexer used reference by local sense amplifier for selected bit line coupled memory cell read. Since reference signal received circuitry that same same symmetric location selected signal, mismatches caused by dummy elements being located away active elements are greatly reduced. In another aspect, reference cell current generated globally, such by circuit along array periphery, mirrored current source into array.

The scope invention defined by claims, which are incorporated into this section by reference. A more complete understanding embodiments present invention afforded those skilled art, well realization additional advantages thereof, by consideration following detailed description one or more embodiments. Reference made appended sheets drawings that first described briefly.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 diagram portion conventional divided bit line memory array architecture, with associated read circuitry;

FIG. 2 diagram portion memory array architecture with two-stage sensing scheme according one embodiment present invention.

Embodiments present invention their advantages are best understood by referring detailed description that follows. It should appreciated that like reference numerals are used identify like elements illustrated one or more figures.

DETAILED DESCRIPTION

According one aspect present invention, memory cell array physically divided into even number sectors, with each pair sectors having local read circuitry comprising local sense amplifiers multiplexers. Each sector divided into groups memory cells, with each group further divided into sub-groups memory cells. Each sub-group associated with multiplexer local sense amplifier, with sense amplifier being shared with another sub-group corresponding sector. A global sense amplifier associated with each group memory cells local sense amplifiers. The local sense amplifiers sense local data lines within sectors, while global sense amplifiers sense global data lines associated with each group memory cells. Thus, two-stage sensing scheme employed.

The present invention also takes advantage physical space outside memory array. Consequently, transistor size local sense amplifiers properly designed provide sufficient current charge or discharge global data lines timely manner for second stage sensing. This decreases overall sensing time. Further, for each pair sectors, one sector not selected (i.e., one not containing memory cell read) used reference for local sense amplifiers. As result, there very small mismatch, if any, for capacitance associated with signals local sense amplifiers.

FIG. 2 portion memory array 200 according one embodiment present invention. Memory array 200 includes N sectors 202 , with each pair sectors associated with one read circuitry 204 . Each sector divided into one or more groups 206 memory cells 208 (exaggerated size for clarity), only one which shown for illustration. Each group 206 memory cells, turn, divided into one or more sub-groups 210 . Sectors, groups, sub-groups contain rows columns memory cells. Memory cells 208 any type suitable memory storage element, such as, but not limited to, nonvolatile memory cells, flash memory cells, floating gate EPROMs EEPROMs, one or more PMOS transistors, one or more NMOS transistors, NAND circuits, NOR circuits. A source or drain terminal each memory cell connected bit line 212 . Conventional circuitry (not shown), such word line decoders bit line decoders, used for selecting or unselecting memory cell.

Each sub-group 210 memory cells shares single multiplexer 214 . For example, if sub-groups contain 16 memory cells 208 row, multiplexer 214 16:1 multiplexer, with 16 inputs multiplexer being 16 bit lines associated with each 16 memory cells. The output each multiplexer 214 coupled input local sense amplifier 216 by local data lines LDL. The other input sense amplifier 216 output corresponding multiplexer 214 other one two sectors pair. Each local sense amplifier 216 thus shared by numerous memory cells for sensing their stored logic values. Local sense amplifier 216 outputs two signals, “true” signal complement. Conventional sense amplifier circuits used, such ones that include differential amplifier circuit that generally senses current (or voltage) differential between current (or voltage) appearing bit line connected selected memory cell reference line. The sense amplifier then provides sense output signal that represents stored logic value. Various types sense amplifiers used, such conventional differential sense amps one described commonly-owned U.S. patent application Ser. No. 10/390,136, entitled “Sense Amplifier Circuit Method”, filed Mar. 14, 2003 by Shiou-Yu Alex Wang et al., which incorporated by reference its entirety.

The “true” output each local sense amplifier 216 group 206 connected together by wired-OR, complement output each local sense amplifier 216 same group 206 connected together by wired-OR. The wired-OR connection true outputs forms “true” global data line 218 , wired-OR connection complement outputs forms “complement” global data line 220 . The true complement global data lines span entire height array or N sectors, with true global data line 218 complement global data line 220 used carry signals global sense amplifier 222 , which amplifies signal local sense amplifiers. Global sense amplifier 222 senses difference between its two input signals produces output representative logic value stored selected memory cell. Global sense amplifier 222 types similar local sense amplifier 216 or any other suitable type sense amplifier circuit. Thus, there one global sense amplifier 222 for each group 206 memory cells one local sense amplifier 216 for each sub-group 210 memory cells.

For example, for 2 Meg bit sector 202 with 512 rows (or word lines) memory cells 208 , there are 4096 (2M/512) columns memory cells 4096 bit lines 212 . Assuming each sub-group 210 sector 16*512 memory cells or 16 columns each group 206 32 sub-groups 210 , then each sector 8 (4096/16/32) groups 206 8 global sense amplifiers 222 . Each group 206 32 pairs 16:1 multiplexers 214 32 local sense amplifiers 216 . Any division sub-groups groups within sector made increase or decrease granularity sector or array. Advantages this discussed below.

According one aspect present invention, two-stage sensing performed for read operation, with local sense amplifiers 216 doing first stage local sensing global sense amplifiers 222 doing second stage global sensing. For example, if particular memory cell 208 third sector 202 selected read, various decoder circuitry turns off unselected memory cells appropriate local sense amplifier 216 compares signal selected bit line signal “reference” bit line. The reference bit line corresponding unselected multiplexer 214 associated with fourth (or unselected) sector 202 . The global sense amplifier 222 associated with group containing selected memory cell then senses difference between signal carried associated global data line 218 complementary global data line 220 .

One advantage present invention that sense time reduced compared conventional architectures. The signal development time associated with scheme FIG. 2 expressed follows:
t SD , total = C GDL · Δ ⁢ ⁢ V2 I SA1 + C LDL · Δ ⁢ ⁢ V1 I cell + C BLMUX · Δ ⁢ ⁢ V1 I cell + C BL · Δ ⁢ ⁢ V1 I cell = t SD , GDL + t SD , LDL + t SD , BLM + t SD , BL , ( 3 )

where ΔV 2 change signal level needed developed for global sense amplifier produce correct output corresponding output active local sense amplifier, ΔV 1 change signal level needed developed for local sense amplifier produce correct output corresponding stored data selected memory cell, I SA1 local sense amplifier drive current, I cell cell current, t SD,GDL time it takes I SA1 develop ΔV 2 global data line, t SD,BLM time it takes I cell develop ΔV 1 capacitance associated with bit line multiplexer, t SD,BL time it takes I cell develop ΔV 1 bit line. The signal development time for prior art scheme, expressed equation (2), sum t SD,DL +t SD,BLM +t SD,GBL +t SD,SBL . The signal development time t SD,SBL same signal development time t SD,BL if sector size made same both present invention prior art for comparison purposes. Therefore, difference between total signal development time present invention prior art scheme with t SD,GDL , t SD,LDL , t SD,BLM , t SD,DL t SD,GBL . However, signal development time t SD,GDL inversely proportional current I SA1 local sense amplifiers 216 . By increasing size local sense amplifiers 216 , which possible since local sense amplifiers located along periphery array, drive current increased, resulting signal development time t SD,GDL smaller than t SD,GBL . As shown FIG. 2, local sense amplifiers 216 placed between pairs sectors 202 along row direction, according one embodiment.

Thus, current driving capability first stage local sense amplifier not limited by memory cell made larger than memory cell current improve speed. This also accomplished by increasing granularity or making granularity finer by increasing number local sense amplifiers. This allows multiplexers 216 narrower width, which turn allows simpler single stage multiplexer design with smaller parasitic capacitance. Consequently C BLM t SD,BLM also become smaller. Finer granularity also allows shorter local data lines which make C LDL t SD,LDL smaller than C DL t SD,DL prior art scheme. Smaller t SD,GDL , t SD,BLM , t SD,LDL all contribute reduction total signal development time t SD , turn improves read performance.

Another advantage present invention improvement matching bit line loading seen by local sense amplifiers 216 . Local sense amplifier 216 one its inputs bit line 212 carrying signal corresponding stored data selected memory cell. The other input reference bit line corresponding multiplexer unselected (or oppositely located) sector. Because two sectors sharing circuitry 204 are same multiplexers 214 associated with bit lines are same, with symmetrical placement relation local sense amplifiers 216 , very close match bit line loading possible. This reduces signal development needed by local sense amplifier produce correct output consequently improves read performance.

In one embodiment, common reference current generation circuit coupled bit lines used provide reference current for unselected bit line. For example, if 6 μA current generated for selected or “on” memory cell 0 μA current associated with unselected or “off” memory cell, reference current 3 μA may selected. The reference current generation circuit may global circuit, which switches or select transistors determine whether or not particular bit line coupled current. In other embodiments, reference current generation circuit may comprised multiple current generators located various portions array. In one embodiment, reference current generation circuit or circuits are placed along periphery array, which allows more flexibility placement due less space limitations than interior array. Current-to-voltage converters may used generate output reference voltage having voltage level that based upon value reference current output cell voltage having voltage level that corresponds current selected memory cell.

Thus, present invention improves read performance scalability by adding first stage sensing circuitry for each pair sectors, using global sense amplifiers second stage amplify output first stage. This allows larger first stage drive current than cell current by choosing proper size first stage sense amplifiers, and/or narrower width multiplexers first stage. The larger drive current reduces signal development time needed for global data lines with global sense amplifiers. Bit line matching for reference signal also increased since reference signal generated by circuitry that same configuration, size, layout circuitry used carry signal for selected memory cell read.

Embodiments described above illustrate but do not limit invention. It should also understood that numerous modifications variations are possible accordance with principles present invention. Accordingly, scope invention defined only by following claims.