Bit switch voltage drop compensation during programming in nonvolatile memory

What claimed is:




1. A semiconductor memory device, comprising: plurality bit lines coupled supply voltage node, each said bit lines comprising respective plurality memory cells coupled said supply voltage node through respective bit switch, wherein group said memory cells are addressable together for programming or overerase correction; means for adjusting supply voltage said supply voltage node responsive detection total bit line current provided said plurality bit lines least partially compensate for voltage drop across said bit switches, said voltage drop being dependent least part said total bit line current, said adjustment comprising increasing said supply voltage responsive detected increase said total bit line current decreasing said supply voltage responsive detected decrease said total bit line current, wherein said adjusting means comprises: differential amplifier having output coupled said supply voltage node; reference voltage generating circuit having output coupled reference voltage input said differential amplifier, said reference voltage generating circuit comprising resistance circuit coupled current mirror circuit, said current mirror circuit configured mirror said total bit line current with reduction ratio.


2. The semiconductor device claim 1, wherein said adjusting means maintains bit line voltage memory cell said plurality memory cells that substantially constant during programming or overerase correction.


3. The semiconductor memory device claim 1, wherein said semiconductor memory device flash memory device comprising flash memory cells organized array I/O blocks, each I/O block comprising plurality columns plurality rows, said array I/O blocks comprising said plurality bit lines.


4. A semiconductor memory device, comprising: plurality bit lines coupled supply voltage node, each said bit lines comprising respective plurality memory cells coupled said supply voltage node through respective bit switch, wherein group said memory cells are addressable together for programming or overerase correction; means for detecting total bit line current provided said plurality bit lines; means for adjusting said supply voltage responsive said detected total bit line current least partially compensate for voltage drop across said bit switches, said voltage drop being dependent least part said total bit line current, wherein said supply voltage comprises fixed reference voltage component variable voltage component responsive said detected total bit line current, said semiconductor device further comprising means for incrementally adjusting relationship between said variable component said total bit line current response respective memory cells said group memory cells reaching programmed state, wherein said adjusting means comprises reference voltage generating circuit comprising tunable resistance circuit coupled current mirror circuit, said current mirror circuit configured mirror said total bit line current with reduction ratio.


5. The semiconductor device claim 4, further comprising means for adjusting resistance said tunable resistance circuit responsive plurality control signals indicative whether each said respective cells said group memory cells programmed state.


6. The semiconductor device claim 5, wherein said relationship adjusted after each respective cell said group memory cells reaches said programmed state.


7. The semiconductor device claim 4, further comprising means for generating said variable voltage component.


8. The semiconductor memory device claim 4, wherein said semiconductor memory device flash memory device comprising flash memory cells organized array I/O blocks, each I/O block comprising plurality columns plurality rows, said array I/O blocks comprising said plurality bit lines.


9. A semiconductor memory device comprising flash memory cells organized array comprising plurality columns plurality rows, said plurality columns comprising plurality bit lines each comprising respective one memory cells coupled supply voltage through respective bit switch, wherein group said memory cells are addressable together for programming, said semiconductor device further comprising: means for detecting total bit line current provided plurality bit lines associated with said group memory cells; regulated supply voltage source for providing said supply voltage, said supply voltage comprising fixed reference voltage component variable voltage component responsive said detected total bit line current, wherein said supply voltage adjusted track changes total bit line current provided said plurality bit lines associated with said group; means for adjusting, response respective memory cells reaching programmed state, relationship between said variable voltage component said total bit line current, said adjusting means comprising reference voltage generating circuit comprising tunable resistance circuit coupled current mirror circuit, said current mirror circuit configured mirror said total bit line current with reduction ratio.


10. The semiconductor device claim 9, further comprising means for adjusting resistance said tunable resistance circuit responsive control signal indicative whether each said respective cells are programmed state.


11. The semiconductor device claim 10, wherein said relationship adjusted after each respective cell reaches said programmed state.


12. A semiconductor memory device, comprising: bit line; memory cell bit switch coupled between said memory cell supply voltage node; current mirror circuit configured mirror bit line current through said memory cell with reduction ratio; voltage source having output coupled said supply voltage node responsive reference voltage; reference voltage generator circuit having output coupled reference voltage input said voltage source, said reference voltage generator circuit comprising resistance circuit coupled said current mirror circuit, wherein said reference voltage generator circuit provides reference voltage for said voltage source that responsive said mirrored bit line current, whereby said supply voltage said supply voltage node adjusted responsive said bit line current least partially compensate for voltage drop across said bit switch, said voltage drop being dependent least part said bit line current.

FIELD OF THE INVENTION

The present invention relates integrated circuit memory including array memory cells circuitry for compensation for voltage drops during programming.

BACKGROUND OF THE INVENTION

FIG. 1 shows typical configuration for integrated circuit including flash EEPROM memory array 100 circuitry enabling programming, erasing, reading, overerase correction for memory cells array 100 . The flash EEPROM array 100 composed individual cells, such cell 102 . Each cell drain connected bitline, such bit line 104 , each bitline being connected bitline switch circuit 106 column decoder 108 . Sources array cells are connected each other VSL, which common source signal, while their gates are each connected by wordline row decoder 110 .

The row decoder 110 receives voltage signals power supply 112 distributes particular voltage signals wordlines controlled by row address received processor or state machine 114 . Likewise, bitline switch circuit 106 receives voltage signals power supply 112 distributes particular voltage signals bitlines controlled by signal processor 114 . Voltages provided by power supply 112 are provided controlled by signals received processor 114 .

The column decoder 108 provides signals particular bitlines sense amplifiers or comparators 116 controlled by column address signal received processor 114 . The power supply 112 supplies voltages column decoder 108 bit lines 104 . The sense amplifiers 116 further receive signal reference cells reference array 118 . With signals column decoder 108 reference array 118 , sense amplifiers 116 then each provide signal indicating state bitline relative reference cell line which it connected through data latches or buffers 120 processor 114 .

To program cell flash memory array 100 , high gate-to-source voltage pulses are provided cell power supply 112 while source cell grounded. For instance, during programming multiple gate voltage pulses typically 10 V are each applied for approximately three six microseconds cell, while drain voltage cell set 4.5 V its source grounded. The large gate-to-source voltage pulses enable electrons flowing source drain overcome energy barrier produce “hot electrons,” some which are accelerated across thin dielectric layer enabling electrons driven onto floating gate cell. This programming procedure, termed “hot electron injection” results increase threshold voltage for cell, threshold being gate-to-source voltage required for cell conduct.

To erase cell flash memory array 100 , procedure known Fowler-Nordheim tunneling utilized wherein relatively high negative gate-to-source voltage pulses are applied for few tenths second each. For instance, during erase multiple gate voltage pulses −10 V are applied cell, while source cell set 5.5 V its drain floating. The large negative gate-to-source voltage pulses enable electrons tunnel floating gate cell reducing its threshold.

After erasure, there concern with “overerase.” Overerased cells threshold voltage that too low provide leakage current even when gate-to-source voltage 0V. The cell leakage form non-negligible bit line current, which leads reading programming errors. Therefore, overerase correction performed reduce this bit line current. During overerase correction, all cells bit line flash memory array 100 same gate-to-source voltage with source grounded. The drain voltage cell set around 5V. Again, hot electrons injected into floating gate raise threshold voltages cells.

During programming, bit line current bit line composed cell current with cell biased programming condition any cell currents provided by unselected cells bit line. In general, unselected cells gate-to-source voltage ground level. During overerase correction, bit line current composed all cell currents coming all cells connected bit line. If overerase correction done by bit line, all cells equal gate-to-source voltages. If overerase correction done by cell, selected cell different gate-to-source voltage other cells.

To represent data bit, floating gate cell programmed or erased described above. In programmed state, threshold voltage cell typically set greater than 5.0 volts, while threshold voltage cell erased state typically limited below 3.0 volts. To read cell, control gate voltage between 3.0 6.5 volts, typically 5 V, applied. The 5 V read pulse applied gate array cell well cell reference array 118 having threshold near 3.5 V. In programmed state with array cell array 100 having threshold above 5.0 V, current provided by reference cell with threshold 3.5 V greater indicating programmed cell exists. In erased state with threshold cell array 100 below 3.0 V, current provided by array cell greater than reference cell with threshold 3.5 V indicating erased cell. To verify programming or erase, read voltage similarly applied both cell array cells reference array 118 . For programming, reference cell having threshold 5.0 V used for comparison, while for erase, reference cell having threshold 3.0 V used for comparison.

FIG. 2 circuit diagram portion flash memory, specifically illustrating two bit lines 104 each including two cells 102 associated circuitry for generating bit line voltages VBL (shown VBLo through VBLn) respective drains cells 102 during programming overerase correction. The common source line shown grounded. Although only two bit lines 104 two word lines are illustrated, it should understood that any number bit lines words lines, thus any number cells, may included memory array. Respective word line signals WLo through WLn are coupled control gates cells 102 . There are multiple bit lines selected by column decoder (FIG. 1), which activate bit switches 124 associated with each bit line. Once corresponding bit switch 124 turned on, corresponding bit line 104 activated cell 102 activated via word line signal.

The memory array also typically includes multiple I/Os, such eight I/Os byte mode 16 I/Os word mode. Each I/O includes multiple bit lines 104 one bit line selected each I/O for reading or programming, i.e., one bit line each selected 8 I/Os byte mode (for total 8 bit lines eight bits) one bit line each selected 16 I/Os word mode (for total 16 bit lines 16 bits) for reading or programming. Each I/O corresponds one internal data line signal, DL (shown DL[ 0 ] through DL[n]), multiple bitlines. Signal DL[n] global signal shared by local bit lines with common I/O, DL[ 0 ] global signal shared by local bit lines with common I/O, although FIG. 2 illustrates only one bit line 104 per I/O. If “0” programmed selected cell 102 selected bit line 104 selected I/O, respective PMOS QPL associated with I/O turned on. If “1” programmed cell, corresponding PMOS QPL I/O turned off.

Power supply 112 (also shown FIG. 1) may include charge pump circuit or external power supply supply bit line current bit line needed during programming or overerase correction. The supply voltage VDQ 1 regulated target drain voltage value VDQ 2 by, for example, differential amplifier 122 . Bit switches 124 , illustrated pass gate transistors QBS 0 , QBS 1 , QBS 2 , are turned by being biased high voltage level VPP by addressed column decoder 108 transfer voltage VDQ 2 local bit line 104 . In illustrated example, each bit switch 124 includes three MOS pass transistors, but number pass transistors vary chip design chip design.

The target value for voltage VDQ 2 set ((Ra+Rb)/Ra)*VR. VR reference voltage provided by, for example, reference voltage sub-circuit (not shown). A capacitor 126 coupled between node VDQ 2 ground. This capacitor reduces variation VDQ 2 when its source, VDQ 1 , pumped. A leakage path circuit discharges VDQ 2 once VDQ 2 over target value, particularly during time when VDQ 2 initially generated by charge pump circuit, prevent overshoot. A capacitor 130 also connected between gate PMOS QP 0 node VDQ 2 . Capacitor 130 responses VDQ 2 QP 0 real time. The bit switches 124 are shown biased with high voltage level VPP allow passing VDQ 2 local bit lines during programming or overerase connection. The transistor size bit switch 124 typically limited save size.

During operation, there voltage drop across bit switch 124 PMOS QPL each bit line when current flows therethrough. The magnitude voltage drop depends magnitude current through each cell 102 , i.e., larger bit line current, larger voltage drop. This voltage drop decreases local bit line voltage VBL (shown VBLo through VBLn FIG. 2) below target level VDQ 2 . The programming capability significantly reduced during initial programming stage because increased current cells 102 . Overerase correction also degraded. As cell gradually programmed, cell gains electrical charge cell current decreases gradually. The local VBL raises approach VDQ 2 local bit line current decreases.

The voltage drop VBL also impact overerase correction. The efficiency overerase correction reduced significantly may result failure, i.e., cell cannot overerase corrected successfully limited time duration set by design.

The circuit programming technique illustrated FIG. 2 described above does not provide fixed VBL during programming each cell 102 . If VDQ 2 designed high compensate for voltage drop across bit switches 124 , there are reliability concerns when bit line current reduced through programming or overerase correction. The reliability concerns include stressing out interface state degrading endurance cycle cell. If VBL raised too close VDQ 2 , VBL cause soft program non-selected cells selected bit line. Generated hot holes impact Si—SiO 2 interface generate interface states. The interface states impact cell threshold voltage change erasing characteristics cell well programming.

Therefore, there remains need for circuit methodology for providing bit line voltage memory cell or cells that insensitive cell current.

SUMMARY OF THE INVENTION

A method provided regulating supply voltage for providing bit line voltage semiconductor memory device where bit line voltage provided memory cells bit line supply voltage through bit switch. A bit line current provided memory cells detected. The supply voltage adjusted responsive detected bit line current least partially compensate for voltage drop across bit switch where voltage drop dependent least part bit line current.

The above other features present invention better understood following detailed description preferred embodiments invention that provided connection with accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings illustrate preferred embodiments invention, well other information pertinent disclosure, which:

FIG. 1 shows typical prior art configuration for integrated circuit including flash EEPROM memory array circuitry enabling programming, erasing, reading overerase correction array;

FIG. 2 illustrates prior art circuitry for providing bit line voltage for programming overerase correction cells flash EEPROM memory array;

FIG. 3 illustrates circuit design for providing fixed bitline voltage;

FIGS. 4–7 illustrate embodiments circuit design FIG. 3.

DETAILED DESCRIPTION

FIG. 3 illustrates circuit for providing bit line voltage VBL memory cells 102 bit lines 104 that substantially insensitive changes bit line current. The schematic FIG. 3 same circuit schematic FIG. 2, like components are referred with like references, except capacitors 126 130 leakage path circuit 128 are not shown array 1000 includes bit line current detector reference voltage tuner circuit 200 (hereinafter Detector Tuner Circuit 200 ), which provides reference voltage VRP for differential amplifier 122 . Detector Tuner Circuit 200 detects total bit line current I provided cells 102 transistor QPO adjusts level reference voltage VRP according magnitude total bit line current I compensate for voltage drops across bit switches 124 I/O selection transistors QPL. The reference voltage VRP input differential amplifier 122 control level VDQ 2 thus level local bit line voltages VBL. When large total bit line current flows through PMOS QP 0 , VRP raised raise VDQ 2 , thereby countering corresponding larger voltage drop across bit switches 124 raising local VBL levels. This approach illustrated more detail embodiment FIG. 4.

Referring FIG. 4, Detector Tuner Circuit 200 includes current mirror circuit, such small PMOS transistor QP 1 , that mirrors total bit line current I with fixed reduction ratio M. The reduced current i equals I (total bit line current)/M. In one embodiment, M selected between about 10 50. A resistor Rt (which preferably tunable discussed below) coupled between fixed reference voltage VR current mirror add voltage i*Rt VR, thereby providing tuned reference voltage VRP, which dependent fixed voltage VR total bit line current I. In essence, voltage VRP includes fixed component (VR) variable component (i*Rt) responsive changes total bit line current I.

As noted above, reference voltage VRP used control level VDQ 2 through differential amplifier 122 . PMOSs QP 2 through QPN Detector Tuner circuit 200 may utilized raise voltage VDP close VDQ 2 , making mirror QP 1 operate same bias condition QP 0 close perfect mirror. Because VRP dependent part total bit line current I, large total bit line current I produces proportionately large voltage addition VR, i.e., amount i*Rt (or (I/M)*Rt). This voltage addition represented VDQ 2 compensates for voltage drops across voltage switches activated bit lines, particularly initial programming stage when VBL drop below its target value because large voltage drops. As cell current decreases through programming or overerase correction, total bit line current I decreases, causing decrease mirrored current i, causing decrease voltage i*Rt added VR, thus voltages VRP VDQ 2 , thereby preventing stressing cells 104 . The determination PMOS size resistance value Rt circuit 200 are discussed below.

Assume initially that multiple bit lines 104 multiple I/Os are modeled single bit line. The equivalent resistance multiple, parallel bit switches 124 PMOSs QPL that are active during any one programming event Req. The total current I flows through Req. Assuming VD=VRP, then (Ra/(Ra+Rb))*VDQ 2 =VRP. VRP also equals (I/M)*Rt+VR. VDQ 2 also equal VBL+I*Req. Therefore, ((Ra/(Ra+Rb))*(VBL+I*Req)=VR+(I/M)*Rt. The bit line voltage VBL typically set equal ((Ra+Rb)/Ra)*VR, which fixed voltage. From this equation, it known that ((Ra/(Ra+Rb))*I*Req=(I/M)*Rt. Therefore, Rt=((M*Ra)/(Ra+Rb))*Req. Assuming further programming condition where only one cell being programmed, Req set Req/cell—the equivalent resistance QPL bit switch 124 selected bit line 104 . Transistors QP 2 through QPn are preferably sized large enough negligible resistance compared with Rt.

It preferred that voltage node VDP near VDQ 2 , thereby providing close theoretically perfect current mirror, but this not requirement. Additional PMOS transistors QP 2 through QPn added between node VRP node VDP raise voltage VDP close VDQ 2 thereby place QP 1 bias condition similar QP 0 . The electrical path between nodes VDP VRP must turned on, thereby limiting number PMOSs used Detector Tuner Circuit 200 . The n-well bias PMOS QPn connected node VRP must voltage higher than VRP because PMOS n-well QPn must higher voltage than its source drain avoid turning source p-n junction or drain p-n junction. This voltage referenced voltage VCX.

The total bit line current I decreases initial programming state during programming, individual cells approach programmed state. In addition, total bit line current I decreases once some cells I/Os are programmed, while some cells remain unprogrammed. Programmed cells appear open circuits and/or programmed cells are disconnected node VDQ 2 by opening respective switch QPL after programming. As some cells become programmed, voltage drop across bit switches 124 PMOSs QPL does not change non-programmed cells, but voltage (i*Rt) added VR reduced because reduced value total current I, thereby undesirably reducing VDQ 2 . With VDQ 2 reduced, local VBL voltages cells that are still being programmed may not reach their target level. To eliminate this effect, resistor Rt preferably tunable so that it responsive respective cells reaching their programmed state. As current I decreases incrementally with each cell becoming programmed, resistance resistor Rt increased so that relationship between variable voltage component VRP total bit line current adjusted compensate for lower magnitude total bit line current, although variable voltage component still tracks changes total bit line current real time thereafter. Increasing resistance Rt ensures that variable voltage component VRP not negligible. In one embodiment shown FIG. 5, each I/O feeds back signal PDN represent whether its addressed cell selected bit line programmed state (or bit line any overased cells during overerase correction). The signals PDN are then used tune resistance Rt shown FIG. 5. Signal PDN may generated using reference array 118 sense amplifiers 116 techniques described above that sense whether there bit line current during overerase correction or during programming, or using techniques familiar those art for confirming programmed state cell or presence overerase condition.

The control signals are illustrated FIG. 5 PDN[ 0 ] through PDN[n] tuning circuit 500 Detector Tuner Circuit 200 . Tuning Circuit 500 includes plurality parallel resistors R that may selectively added or removed parallel combination by transistor switches triggered by control signal PDN change resistance Rt. As mentioned above, each signal PDN[ 0 ] through PDN[N] corresponds programmed state addressed cell selected bit line respective I/O or overerase condition bit line respective I/O. If cell respective I/O already programmed state (or bit line does not include any overerased cells), respective PDN[n] tuning circuit 500 set low state, thereby opening respective switch removing respective resistor R parallel combination tuning circuit 500 increasing resistance Rt tuning circuit 500 , thereby keeping voltage i*Rt, which still tracks changes total bit line current I, meaningful level despite incremental decreases total bit line current I cells become programmed or overerase corrected. In essence, when current i decreases each cell becomes programmed, resistance Rt increases maintain relative magnitude voltage i*Rt, which turn effects VRP (i.e., VR+i*Rt). It important note, however, that embodiment FIG. 5, resistance Rt changed incrementally, not constantly with changes current I. Once Rt changed because cell reaches its programmed state, Rt fixed until next cell becomes programmed. VRP continues track changes current i rate set by value Rt until Rt changed. Once next cell becomes programmed, corresponding resistor R removed parallel combination circuit 500 , thereby increasing resistance Rt amount that variable component VRP tracks real time changes current i. Increasing resistance Rt incrementally each cell becomes programmed assures that voltage VRP continues track changes total bit line current I meaningful way.

Assume, for example, that programming occurs bytes. If five eight cells remain programmed, then five eight signals PDN trigger switches circuit 500 so that Rt equals equivalent resistance five resistors R coupled parallel. While five cells are being programmed, VRP, thus VDQ 2 , track real time changes current I amount set by temporarily fixed value Rt. Once cell five cells becomes programmed, corresponding signal PDN opens switch circuit 500 , thereby increasing value equivalent resistance Rt amount by which VRP VDQ 2 track changes current I for programming remaining four cells. In one embodiment, per formula derived for Rt above, each resistor R set equal M*(Ra/(Ra+Rb))*Req/cell.

As noted above, bit switch path turned off for programmed cell or I/O by signal PD[n] coupled control gate PMOS QPL. Each signal PD inverse state respective signal PDN its logical high set VDQ 2 logical low VSS.

The memory circuit FIG. 5, although not shown, may still include leakage path node VDQ 2 ground shown FIG. 2 reduce any initial overshoot VDQ 2 discussed above connection with FIG. 2. This current, however, mirrored circuit 200 by bit line current detector PMOS QP 1 . The effect this leakage current neutralized by turning leakage current circuit for time interval, for example, 1 μs, stabilize VDQ 2 level turning off leakage current circuit thereafter. A timing circuit (not shown) may used control this time duration. The timer that generates control signals for timing program pulses, overerase pulses erase pulses may used. During this interval, input differential amplifier 122 set VR rather than VRP, essentially disconnecting Detector Tuner Circuit 200 differential amplifier 122 setting VDQ 2 constant voltage. After this time interval, VRP connected differential amplifier and, optionally, small leakage path circuit turned replace original leakage path circuit for avoiding VDQ 2 overshoot. The leakage path circuit may comprise, one ordinary skill familiar with prior art circuit FIG. 2 recognize, one or more NMOS transistors coupled series node VDQ 2 . If voltage VDQ 2 too high, current sink through NMOS transistors ground. Once VDQ 2 level stabilized, leakage current reduced by connecting smaller NMOS transistors node VDQ 2 .

FIG. 6 illustrates that resistors R tuning circuit 500 A implemented transistors with sizes that conform ratio (Ra/(Ra+Rb))*M*the equivalent resistance transistors bit switches 124 I/O switch QPL bit line. This design advantages temperature compensation over using resistors, i.e., transistors same temperature coefficient transistors bit switches.

Tables 1-1 1-2 below illustrate results software simulation prior art circuit FIG. 2, where VCC (the power supply voltage), temperature reference voltage VR are set indicated. Column “G” indicates gate voltage PMOS QP 0 . The tables illustrate two conditions—(1) there only one erased cell programmed, or one bit line overerase corrected, (2) there are eight erased cells programmed or eight bit lines overerase corrected. The tables illustrate that bit line voltage VBL drops between about 0.4 0.6 volts compared with regulated, fixed VDQ 2 when between about 2.5–3.3 mA current flows through bit line or bit lines. The notation “0 mA” represents that all cells are programmed state.

TABLE 1-1
VCC/Temp = 3.6 V/0° C.; VR = 1.2 V.
No. I/O	total bit line
VDQ1	VDQ2	be programmed	current	G	VDP
6 V	4.67 V	1	0	mA	5.2	V	4.09 V
4.66 V	0.315	mA	5.07	V	4.46 V
4.67 V	8	0	mA	5.2	V	4.09 V
4.66 V	2.53	mA	4.81	V	4.91 V
8 V	4.69 V	1	0	mA	7.24	V	4.08 V
4.67 V	0.317	mA	7.10	V	4.45 V
4.69 V	8	0	mA	7.24	V	4.07 V
4.65 V	2.52	mA	6.86	V	4.90 V

TABLE 1-2
VCC/Temp = 2.5 V/90° C.; VR = 1.2 V.
No. I/O	Total cell
VDQ1	VDQ2	be programmed	current	G	VDP
6 V	4.68 V	1	0	mA	5.4	V	3.26	V
4.66 V	0.344	mA	5.22	V	3.8	V
4.68 V	8	0	mA	5.4	V	3.26	V
4.65 V	2.74	mA	4.89	V	4.36	V
8 V	4.70 V	1	0	mA	7.44	V	3.24	V
4.67 V	0.344	mA	7.25	V	3.75	V
4.70 V	8	0	mA	7.44	V	3.24	V
4.65 V	2.74	mA	6.94	V	4.35	V

Tables 2-1 2—2 below illustrate results software simulation circuit FIG. 6, with resistors used simulate bit switch resistances. The tables illustrate two conditions—(1) there only one erased cell programmed, or one bit line overerase corrected, (2) there are eight erased cells programmed or eight bit lines overerase corrected. Tables 2-1 2—2 illustrate that VBL difference when total bit line current increased reduced by change VRP, thus VDQ 2 , total bit line current increased or decreased. The simulation illustrates that change VBL due changes bit line current less than or equal about 0.17 volts for each simulation. The simulation assumed that temperature coefficient resistance Rt 1000 ppm/0° C. The “VBL” voltage chart shows bit line voltage bit line with non-zero bit line current (i.e., bit line being programmed or overerase corrected) for bit line with zero bit line current QPL “on”. The VBL voltage VDQ 2 for bit line with zero bit line current QPL “on”.

TABLE 2-1
VCC/Temp = 3.6 V/0° C.; VR = 1.2 V.
No. I/O	total bit line
VDQ1	VDQ2	be programmed	VRP	current	VBL	G	VDP
6 V	4.76 V	1	1.22 V	0	mA	4.76 V	5.2	V	4.12	V
5.24 V	1.34 V	0.33	mA	4.79 V	5.05	V	4.63	V
4.68 V	8	1.20 V	0	mA	4.68 V	5.2	V	4.09	V
5.12 V	1.32 V	2.59	mA	4.68 V	4.78	V	5.0	V
8 V	4.77 V	1	1.22 V	0	mA	4.77 V	7.23	V	4.11	V
5.23 V	1.34 V	0.33	mA	4.78 V	7.09	V	4.61	V
4.70 V	8	1.20 V	0	mA	4.70 V	7.24	V	4.08	V
5.09 V	1.31 V	2.61	mA	4.66 V	6.84	V	4.98	V

TABLE 2-2
VCC/Temp = 2.5 V/90° C.; VR = 1.2 V.
No. I/O	total cell
VDQ1	VDQ2	be programmed	VRP	current	VBL	G	VDP
6 V	4.76 V	1	1.22 V	0	mA	4.76 V	5.4	V	3.29 V
5.36 V	1.37 V	0.36	mA	4.71 V	5.19	V	4.02 V
4.69 V	8	1.20 V	0	mA	4.69 V	5.4	V	3.27 V
5.14 V	1.36 V	2.87	mA	4.65 V	4.83	V	4.53 V
8 V	4.77 V	1	1.22 V	0	mA	4.77 V	7.43	V	3.27 V
5.22 V	1.33 V	0.36	mA	4.60 V	7.24	V	3.91 V
4.71 V	8	1.20 V	0	mA	4.71 V	7.44	V	3.24 V
5.21 V	1.34 V	2.88	mA	4.60 V	6.91	V	4.47 V

Tables 2-1 2—2 below illustrate results software simulation circuit FIG. 6, with resistors used simulate bit switch resistances. The tables illustrate two conditions —(1) there only one erased cell programmed, or one bit line overerase corrected, (2) there are eight erased cells programmed or eight bit lines overerase corrected. Tables 2-1 2—2 illustrate that VBL difference when total bit line current increased reduced by change VRP, thus VDQ 2 , total bit line current increased or decreased. The simulation illustrates that change VBL due changes bit line current less than or equal about 0.17 volts for each simulation. The simulation assumed that temperature coefficient resistance Rt 1000 ppm/°C. The “VBL” voltage chart shows bit line voltage bit line with non-zero bit line current (i.e., bit line being programmed or overerase corrected) for bit line with zero bit line current QPL “on”. The VBL voltage VDQ 2 for bit line with zero bit line current QPL “on”.

Tables 3-1 3-2 below illustrate results software simulation circuit FIG. 6, only using transistors simulate bit switch resistances. The tables illustrate two conditions—(1) there only one erased cell programmed, or one bit line overerase corrected, (2) there are eight erased cells programmed or eight bit lines overerase corrected. Tables 3-1 3-2 indicate results that are similar Tables 2-1 2-2 that VBL stays relatively constant (i.e., largest change VBL due change total bit line current was only about 0.2V). The simulation assumed that temperature coefficient resistance Rt 1000 ppm/°C.

TABLE 3-1
VCC/Temp = 3.6 V/0° C.; VR = 1.2 V.
No. I/O	total bit line	G
VDQ1	VDQ2	be programmed	VRP	current	VBL	(gate voltage)	VDP
6.2	V	4.77 V	1	1.22 V	0	mA	4.77 V	5.36 V	4.01	V
5.37 V	1.38 V	0.29	mA	4.97 V	5.16 V	4.61	V
4.68 V	8	1.20 V	0	mA	4.68 V	5.36 V	3.98	V
5.25 V	1.35 V	2.28	mA	4.86 V	4.74 V	5.0	V
8	V	4.80 V	1	1.22 V	0	mA	4.80 V	7.17 V	3.99	V
5.38 V	1.38 V	0.29	mA	4.97 V	6.97 V	4.61	V
4.69 V	8	1.20 V	0	mA	4.69 V	7.17 V	3.97	V
5.24 V	1.35 V	2.28	mA	4.85 V	6.57 V	4.99	V

TABLE 3-2
VCC/Temp = 2.5 V/90° C.; VR = 1.2 V.
No. I/O	total cell	G
VDQ1	VDQ2	be programmed	VRP	current	VBL	(gate voltage)	VDP
6.2	V	4.78 V	1	1.22 V	0	mA	4.78 V	5.56 V	3.11 V
5.48 V	1.41 V	0.31	mA	4.92 V	5.30 V	3.95 V
4.69 V	8	1.20 V	0	mA	4.69 V	5.56 V	3.10 V
5.38 V	1.39 V	2.47	mA	4.83 V	4.75 V	4.47 V
8	V	4.80 V	1	1.22 V	0	mA	4.80 V	7.38 V	3.10 V
5.56 V	1.42 V	0.31	mA	4.98 V	7.11 V	4.00 V
4.68 V	8	1.20 V	0	mA	4.68 V	7.36 V	3.10 V
5.31 V	1.37 V	2.48	mA	4.77 V	6.59 V	4.44 V

FIG. 7 illustrates another embodiment circuit 200 for regulating voltage VDQ 2 dependent total bit line current. In this embodiment, positive input differential amplifier 122 coupled voltage VBLRP. In tuning circuit 500 B, VBLR set VR*(Ra*Rb)/Ra. VBLRP equals VBLR+i*Rt. The circuit FIG. 7 uses VDQ 2 input differential amplifier, e.g., VDQ 2 applied negative input differential amplifier by feedback connection. This circuit same effect controlling VBL circuit FIG. 6 described above. VBLRP reference voltage for generating voltage VDQ 2 . The resistance simulate bit switches larger than bit switches resistance by M times rather than M*Ra/(Ra+Rb). The N-well PMOS QPn connected VBLR should voltage VCXX higher than VBLR for reasons described above connection with voltage VCX FIG. 6.

From foregoing, it should apparent that circuit method are provided that make local bit line voltages substantially insensitive changes total bit line current by compensating for voltage losses bit lines, such losses across bit line switches that activate bit lines, thereby improving programming overerase correction cell endurance. In one embodiment, local bit line voltage VBL varies less than preferably about 0.2V due changes total bit line current provided power supply.

Although invention been described terms exemplary embodiments, it not limited thereto. Rather, appended claims should construed broadly include other variants embodiments invention that may made by those skilled art without departing scope range equivalents invention.