Circuit and method for reducing leakage current in a row driver circuit in a flash memory during a standby mode of operation

What claimed is:




1. A method operating memory device including memory-cell array having plurality memory cells arranged rows columns, each memory cell respective row being coupled associated word line having respective row driver circuit, method comprising detecting first mode operation memory device response first mode operation, activating pull-down transistors row driver circuits floating least some sources pull-down transistors.


2. The method claim 1 wherein first mode comprises low-power mode memory device.


3. The method claim 2 wherein memory device comprises flash memory wherein low-power mode comprises reset/deep power down mode.


4. A method operating flash memory device during standby mode operation, flash memory device including memory-cell array having plurality memory cells arranged rows columns, each memory cell respective row being coupled associated word line having respective row driver circuit, method comprising: detecting active mode operation memory device; during active mode operation, receiving addresses corresponding memory cells accessed, coupling first voltage word line addressed memory cells through pull-up transistor respective row driver circuit access memory cells corresponding row, applying second voltage each word line associated with memory cells not being accessed; detecting standby mode operation; during standby mode operation, coupling gates pull-down transistors row driver circuits first voltage isolating least some pull-down transistors second voltage.


5. The method claim 4 wherein detecting active mode operation comprise detecting inactive standby mode signal.


6. The method claim 4 wherein all pull-down transistors are isolated during standby mode.


7. The method claim 4 wherein isolating least some pull-down transistors second voltage comprises opening switch between pull-down transistors source second voltage.


8. The method claim 4 wherein first voltage comprises supply voltage wherein second voltage comprises ground voltage.

TECHNICAL FIELD

The present invention relates generally integrated circuits, more specifically lowering power consumption integrated circuits during certain modes operation.

BACKGROUND OF THE INVENTION

Many battery-powered portable electronic devices, such laptop computers, Portable Digital Assistants, digital cameras, cell phones like, require memory devices that provide large storage capacity low power consumption. One type memory device that well-suited use such portable devices flash memory, which type semiconductor memory that provides relatively large nonvolatile storage capacity for data. The nonvolatile nature storage means that flash memory does not require power maintain data, appreciated by those skilled art.

A typical flash memory comprises memory-cell array having array memory cells arranged rows columns grouped into blocks. FIG. 1 illustrates conventional flash memory cell 100 formed by field effect transistor including source 102 drain 104 formed substrate 106 , with channel 108 being defined between source drain. Each memory cells 100 further includes control gate 110 floating gate 112 formed over channel 108 isolated channel each other by isolation layers 114 . In memory-cell array, each memory cell 100 given row its control gate 110 coupled corresponding word line WL each memory cell given column its drain 104 coupled corresponding bit line BL. The sources 102 each memory cell 100 given block are coupled together allow all cells block simultaneously erased, appreciated by those skilled art.

The memory cell 100 charged or programmed by applying appropriate voltages source 102 , drain 104 , control gate 110 thereby injecting electrons e − drain 104 channel 108 through isolation layer 114 onto floating gate 112 . Similarly, erase memory cell 100 , appropriate voltages are applied source 102 , drain 104 , control gate 110 remove electrons e − through isolation layer 114 source 102 channel 108 . The presence or absence charge control gate 112 adjusts threshold voltage memory cell 100 this way stores data memory cell. When charge stored floating gate 112 , memory cell 100 does not turn ON when access voltage applied through word line WL control gate 110 , when no charge stored floating gate cell turns ON response access voltage. In this way, memory cell 100 stores data having first logic state when cell turns ON second logic state when cells does not turn ON.

In conventional flash memory, row driver coupled each word line WL memory-cell array operates access memory cells 100 corresponding row response activation signals. FIG. 2 illustrates conventional row driver 200 including PMOS drive transistor 202 NMOS drive transistor 204 coupled series, with supply voltage VX first reference voltage VXGND being applied sources PMOS drive transistor NMOS drive transistor, respectively. The PMOS drive transistor 202 represents “pull-up” transistor for coupling respective WL supply voltage VX NMOS drive transistor 204 represents “pull-down” transistor for coupling respective WL first reference voltage VXGND. The interconnection drains transistors 202 204 define node 206 that coupled corresponding word line WL. A second PMOS transistor 208 NMOS transistor 210 are coupled series, with supply voltage VX second reference voltage XPDACOM being applied sources transistors, respectively. The interconnection drains transistors 208 , 210 defines node 212 that coupled gates drive transistors 202 204 . The transistor 210 receives first activation signal XPDA PMOS transistor 208 receives second activation signal VXDECEN#. Typically, first second reference voltage VXGND XPDACOM are ground while supply voltage VX 5 volts.

In operation, row driver 200 operates select mode activate memory cells 100 (not shown FIG. 2) coupled word line WL operates deselect mode turn OFF or deactivate memory cells coupled word line, now explained more detail. In select mode, VXDECEN# XPDA signals are high, turning OFF PMOS transistor 208 turning ON NMOS transistor 210 , respectively. The node 212 driven low through transistor 210 , turning OFF drive transistor 204 turning ON drive transistor 202 which, turn, drives word line WL high approximately supply voltage VX through transistor 202 . At this point, memory cells 100 (see FIG. 1) coupled word line WL either turn ON or remain OFF, depending whether memory cell been programmed or erased (i.e., depending data stored cell). In this way, address decode circuitry (not shown) flash memory containing row driver 200 activates XPDA signal corresponding row memory cells accessed. In response activated XPDA signal, corresponding row driver 200 drives word line WL high thereby access memory cells 100 corresponding row.

In deselect mode, VXDECEN# XPDA signals are low, turning ON PMOS transistor 208 turning OFF NMOS transistor 201 , respectively. The node 212 driven high through transistor 208 , turning OFF drive transistor 202 turning ON drive transistor 204 which, turn, drives word line WL low approximately ground through transistor 204 . At this point, all memory cells 100 coupled word line WL are turned OFF, regardless whether cell been programmed or erased. Each row driver 200 operates deselect mode when corresponding row memory cells 100 not being accessed.

During normal operation flash memory, each row driver 200 alternately operates either select or deselect mode, depending whether corresponding row memory cells 100 being accessed or not. The normal mode includes operation flash memory during data transfers when memory cells are being programmed erased. All row drivers 200 operate deselect mode during sleep or power-savings mode operation flash memory. As previously mentioned, battery-powered portable electronic devices utilize flash memory, reduce power consumption thereby extend battery life such devices, flash memory typically placed power-savings mode when flash memory not being used. When power-savings mode, row driver 200 operates previously described drive word line WL low deactivate all corresponding memory cells 100 .

When flash memory operating power-savings mode, memory some point activated commence data transfer operations normal mode. For example, portable device flash memory may operate power-savings mode when device turned OFF, activated response user turning ON device. The time required switch power-savings mode active mode ideally minimized so that user does not experience delay due flash memory changing modes operation. Thus, flash memory should able begin transferring data memory cells 100 soon possible after termination power-savings mode. As result, during power-savings mode, charge pump (not shown) that develops supply voltage VX continues operating provide supply voltage VX row drivers 200 . In this way, when power-savings mode terminated, selected row driver 200 may activate corresponding word line WL more quickly than if driver needed wait for charge pump generate supply voltage VX having required magnitude.

Ideally, operation charge pump during power-savings mode consumes no power since all row drivers 200 are driving word lines WL low PMOS drive transistors 202 are turned OFF, previously described. More specifically, during power-savings mode, VXDECEN# XPDA signals are low, driving node 212 high through transistor 208 thereby turning OFF PMOS drive transistor 202 . Due voltages applied source, drain, gate PMOS drive transistor 202 , however, gate induced drain leakage (GIDL) current IGIDL flows through PMOS drive transistor, appreciated by those skilled art. FIG. 3 simplified cross-sectional view PMOS drive transistor 202 illustrating IGIDL current through transistor this situation. A high electric field developed area 300 where gate 302 overlaps drain 304 PMOS drive transistor 202 . The high electric field due supply voltage VX being applied gate 302 ground being applied drain 304 generates IGIDL current. The concept gate induced drain leakage current understood by those skilled art, thus, for sake brevity, not discussed more detail.

During power-savings mode, NMOS drive transistor 204 turned ON response node 212 (FIG. 2) being driven high through transistor 208 . As result, IGIDL current flows through PMOS drive transistor 202 through NMOS drive transistor 204 ground each row driver 200 . While IGIDL current through individual PMOS transistor 202 single row driver 200 small, summation IGIDL currents through all row drivers may relatively large, cause charge pump developing supply voltage VX consume significant amount power during power-savings mode operation. The total current consumed by charge pump actually substantially greater than summation leakage currents IGIDL through row drivers 200 due operating inefficiencies charge pump, appreciated by those skilled art.

There need for row driver having reduced leakage current lower power consumption during power-savings mode operation flash memory or other type memory device containing row driver.

SUMMARY OF THE INVENTION

According one aspect present invention, row driver receives input signal test mode signal, coupled first second voltage sources output coupled word line. The row driver operates active mode responsive test mode signal going inactive couple output either first or second voltage source responsive input signal. The row driver operates standby mode responsive test mode signal going active present high impedance word line.

According another aspect present invention, method operating memory device includes detecting first mode operation memory device. The memory device includes memory-cell array having plurality memory cells arranged rows columns, each memory cell respective row being coupled associated word line. The method further includes floating least some word lines when first mode detected. The memory device may flash memory device first mode may standby mode operation flash memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 simplified cross-sectional view conventional flash memory cell.

FIG. 2 schematic illustrating conventional row driver for accessing data stored memory cell FIG. 1.

FIG. 3 simplified cross-sectional view illustrating gate induced drain leakage current through PMOS drive transistor row driver FIG. 2.

FIG. 4 schematic block diagram illustrating row driver having reduced gate induced drain leakage current according one embodiment present invention.

FIG. 5 functional block diagram illustrating flash memory including row driver FIG. 4.

FIG. 6 functional block diagram illustrating computer system including flash memory FIG. 5.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 4 schematic block diagram illustrating row driver 500 including isolation circuit 502 for reducing gate induced drain leakage current IGIDL row driver during power-savings mode operation according one embodiment present invention. The isolation circuit 502 receives power-savings mode signal PSM, when this signal active isolation circuit breaks current path ground for IGIDL current thereby reduces leakage current row driver 500 approximately zero, described more detail below. The row driver 500 includes components 504 – 514 that are connected operate same way corresponding components 202 – 212 row driver 200 FIG. 2. For sake brevity, detailed operation interconnection these components 504 – 514 not again described detail. In following description, certain details are set forth provide sufficient understanding present invention, but one skilled art appreciate that invention may practiced without these particular details. In other instances below, operation well known components not been shown or described detail avoid unnecessarily obscuring present invention.

In row driver 500 , isolation circuit 502 coupled source NMOS drive transistor 506 receives reference voltage VXGND PSM signal, which generated by circuitry (not shown) flash memory containing row driver 500 . The PSM signal indicates whether flash memory operating normal mode or power-savings mode. When PSM signal inactive, flash memory operating normal mode isolation circuit 502 couples source NMOS drive transistor 506 reference voltage VXGND. In normal mode, row driver 500 then operates same way previously described for row driver 200 FIG. 2. Briefly, this situation, row driver 500 couples word line WL supply voltage VX through transistor 504 when VXDECEN XPDA signals are high, couples word line reference voltage VXGND through NMOS drive transistor 512 isolation circuit 502 when VXDECEN XPDA signals are low.

When PSM signal goes active, flash memory operates power-savings mode isolation circuit 502 presents high impedance source NMOS drive transistor 506 thereby isolate source ground. In power-savings mode, VXDECEN# XPDA signals are low, driving node 514 high through transistor 510 turning PMOS drive transistor 504 OFF NMOS drive transistor 506 ON previously discussed during normal mode. In this situation, current path IGIDL current through PMOS drive transistor 504 NMOS drive transistor 506 reference voltage VXGND “broken” or “opened” by high impedance isolation circuit 502 presents source PMOS drive transistor 506 . The high impedance isolation circuit 502 thereby isolates or “floats” source NMOS drive transistor 506 , preventing IGIDL current flowing. In this way, row driver 500 eliminates IGIDL current normally associated with row driver during power-savings mode operation. One skilled art understand variety different circuits that may utilized form isolation circuit 502 , such transistor or transmission gate other suitable circuits.

In row driver 500 , it should noted that with row driver 500 word line WL no longer driven reference voltage VXGND through NMOS drive transistor 506 conventional row driver 200 FIG. 2. In contrast, during power-savings mode high impedance isolation circuit 502 results word line WL being isolated reference voltage VXGND. With conventional row driver 200 , word line WL was driven ground turn OFF all memory cells coupled word line. The row driver 500 , contrast, takes advantage fact that during power-savings mode word lines WL need not driven ground since none memory cells are being accessed. Moreover, nonvolatile nature storage flash memory cells allows word lines WL float since even if one or more rows memory cells turns ON, data stored those cells not lost.

FIG. 5 functional block diagram flash memory 400 including plurality row drivers 500 FIG. 4. The row drivers are shown contained address decoders 440 , 440 b , which discussed more detail below. The flash memory 400 includes command state machine (CSM) 404 that receives control signals including reset/power-down signal RP#, chip enable signal CE#, write enable signal WE#, output enable signal OE#, where “#” denotes signal being low true. An external processor (not shown) applies command codes data bus DQ 0 –DQ 15 these command codes are applied through data input buffer 416 CSM 404 . A command being applied flash memory 400 includes control signals RP#, CE#, WE#, OE# combination with command codes applied data bus DQ 0 –DQ 15 . The CSM 404 decodes commands acts interface between external processor internal write state machine (WSM) 408 . When specific command issued CSM 404 , internal command signals are provided WSM 408 , which turn, executes appropriate process generate necessary timing signals control memory device 400 internally accomplish requested operation. The CSM 404 also provides internal command signals ID register 408 status register 410 , which allows progress various operations monitored when interrogated by issuing CSM 404 appropriate command.

In response RP# and/or CE# signals, CSM 404 develops PSM signal control mode operation row drivers 500 . In one embodiment, when CE# signal active low, CSM 404 deactivates PSM signal, placing row drivers 500 normal mode operation. When CE# signal inactive high, CSM 404 activates PSM signal thereby places row drivers 500 power-savings mode operation.

The CE#, WE#, OE# signals are also provided input/output (I/O) logic 412 which, response these signals indicating read or write command, enables data input buffer 416 data output buffer 418 , respectively. The I/O logic 412 also provides signals address input buffer 422 order for address signals latched by address latch 424 . The latched address signals are turn provided by address latch 424 address multiplexer 428 under command WSM 406 . The address multiplexer 428 selects between address signals provided by address latch 424 those provided by address counter 432 . The address signals provided by address multiplexer 428 are used by address decoders 440 , 44 b access memory cells memory banks 444 , 444 b that correspond address signals. A gating/sensing circuit 448 , 448 b coupled each memory bank 444 , 444 b for purpose programming erase operations, well for read operations. An automatic power saving (APS) control circuit 449 receives address signals address input buffer 422 also monitors control signals RP#, CE#, OE#, WE#. When none these lines toggle within time-out period, APS control circuit 449 generates control signals place gating/sensing circuits 448 , 448 b power-saving mode operation.

During read operation, data sensed by gating/sensing circuit 448 , 448 b amplified sufficient voltage levels before being provided output multiplexer 450 . The read operation completed when WSM 406 instructs output buffer 418 latch data provided output multiplexer 450 provided external processor. The output multiplexer 450 also select data ID status registers 408 , 410 provided output buffer 418 when instructed do so by WSM 406 . During program or erase operation, I/O logic 412 commands data input buffer 416 provide data signals data register 460 latched. The WSM 406 also issues commands program/erase circuitry 464 which uses address decoder 440 carry out process injecting or removing electrons memory cells memory banks 444 , 444 b store data provided by data register 460 gating sensing circuit 448 . To ensure that sufficient programming or erasing been performed, data comparator 470 instructed by WSM 406 compare or verify state programmed or erased memory cells data latched by data register 460 . During all these modes operation CSM 404 maintains PSM signal inactive so that row drivers 500 operate normal mode previously described.

The flash memory 400 operates standby mode power-savings when RP# CE# signals are both high, operates reset deep power-down mode when RP# signal goes active low. As previously mentioned, one embodiment, response RP# CE# signals going inactive high place memory 400 standby mode, CSM 404 drives PSM signal active, placing row drivers 500 power-savings mode operation thereby reducing power consumed by flash memory standby mode.

It appreciated that embodiment flash memory 400 illustrated FIG. 5 been provided by way example that present invention not limited thereto. Those ordinary skill art sufficient understanding modify previously described flash memory embodiment implement other embodiments present invention. For example, although row drivers 500 are shown being contained decoders 440 , 440 b FIG. 6, row drivers may incorporated into one other circuit blocks, or alternatively, may split among several circuit blocks. The particular arrangement row drivers 500 within memory device matter design preference. Moreover, CSM 404 may also activate PSM signal response other operating modes flash memory 400 , such when RP# signal goes active low place flash memory reset deep-power down mode operation. The row driver 500 may also used other types integrated circuits containing flash memory, also may used other types memory where word lines may floated during certain modes operation realize power savings during such modes operation.

FIG. 6 block diagram computer system 600 including computer circuitry 602 that contains flash memory 400 FIG. 6. The computer circuitry 602 performs various computing functions, such executing specific software perform specific calculations or tasks. In addition, computer system 600 includes one or more input devices 604 , such keyboard or mouse, coupled computer circuitry 602 allow operator interface with computer system. Typically, computer system 600 also includes one or more output devices 606 coupled computer circuitry 602 , such output devices typically being printer or video display. One or more data storage devices 608 are also typically coupled computer circuitry 602 store data or retrieve data external storage media (not shown). Examples typical storage devices 608 include hard floppy disks, tape cassettes, compact disc read-only memories (CD-ROMs), read-write CD ROMS (CD-RW), digital video discs (DVDs). The computer system 610 also typically includes communications ports 610 such universal serial bus (USB) and/or IEEE-1394 bus provide for communications with other devices, such desktop personal computers, digital cameras, digital camcorders. The computer circuitry 602 typically coupled flash memory 400 through appropriate address, data, control busses provide for writing data reading data flash memory.

Even though various embodiments advantages present invention been set forth foregoing description, above disclosure illustrative only, changes may made detail yet remain within broad aspects invention. Therefore, present invention limited only by appended claims.