Integrated circuit memory device with bit line pre-charging based upon partial address decoding

What claimed is:




1. An integrated circuit memory device comprising: array memory cells arranged plurality rows columns having plurality row lines plurality column lines, with cells arranged same row connected by common row line, cells arranged same column connected by common column line; wherein each cell said array being addressed by address signal having plurality bits; sense amplifier circuit connectable one or more said plurality column lines said array; address input terminal for receiving said plurality bits said address signal series; each said column lines connectable first voltage; decoder circuit for receiving said address signal for decoding said address signal each said plurality bits received for disconnecting certain said column lines said first voltage response said decoding; for activating said sense amplifier circuit after all said plurality bits said address signal are received.


2. The memory device claim 1 wherein each said cells non-volatile memory cell.


3. The memory device claim 2 wherein each said non volatile memory cells stacked gate floating gate non-volatile memory cell.


4. The memory device claim 2 wherein each said non volatile memory cells split gate floating gate non-volatile memory cell having first region semiconductor substrate, second region said semiconductor substrate spaced apart said first region by channel region; floating gate for controlling conduction current first portion said channel region; control gate for controlling conduction current second portion said channel region; wherein said control gate separated said floating gate by insulator permitting Fowler Nordheim tunneling electrons said floating gate said control gate.


5. The memory device claim 1 further comprising shift register; said shift register for receiving said plurality bits said address signal.


6. The memory device claim 5 further comprising row decoder for receiving first portion said plurality bits said address signal for decoding said first portion for selecting row line response thereto.


7. The memory device claim 6 wherein said decoder circuit column decoder for receiving second portion said plurality bits said address signal for decoding said second portion for selecting column line response thereto.


8. The memory device claim 1 further comprising multiplexer, wherein said sense amplifier circuit connectable said plurality column lines through said multiplexer.


9. The memory device claim 1 further comprising plurality switches, each interposed between column line said first voltage; wherein each said switches responsive output said decoder circuit.


10. The memory device claim 1 wherein each said column lines connectable first voltage response read command, thereby initiating pre-charging sequence.


11. The memory device claim 1 wherein said address signal having row address portion column address portion, wherein each said row address portion column address portion comprising plurality bits.


12. The memory device claim 11 wherein each said column lines connectable first voltage response first bit said column address portion.


13. A method operating integrated circuit memory device, having array memory cells arranged plurality rows columns, with plurality row lines plurality column lines, with memory cells same row connected by common row line, memory cells same column connected by common column line, wherein each cell said array being addressed by address signal having plurality bits; said memory device further having sense amplifier circuit connectable least one said plurality column lines, said method comprising: receiving said plurality bits said address signal series; pre-charging said plurality column lines said array; selectively deactivating pre-charging another plurality column lines said array, wherein said another plurality column lines are unselected column lines; activating said sense amplifier circuit for detecting state said addressed cell after all said plurality bits said address signal are received.


14. The method claim 13 further comprising: activating said sense amplifier circuit least one clock cycle after pre-charging said plurality column lines said array.

TECHNICAL FIELD

The present invention relates integrated circuit memory device method operating such device wherein memory device, response read command, pre-charges bitlines based upon partial address received through serial line. More particularly, present invention relates serially addressed integrated circuit memory device which column lines are pre-charged based upon partial address further received address bits are used disconnect select column lines pre-charged voltage activate sense amplifier after all address received.

BACKGROUND OF THE INVENTION

Serially addressed integrated circuit memory devices are well known art. See, for example, U.S. Pat. Nos. 5,663,922 6,097,657. As shown U.S. Pat. No. 5,663,922, it well known art decode partial address received by serially addressed integrated circuit memory device activate “read” various portions memory array. This mechanism decoding address signals they are serially inputted increases performance such device by reading soon possible those cells which are selected by partial address. The shortcoming U.S. Pat. No. 5,663,922 that it does not address problem saving power; '922 patent increases total number sense amplifiers activates all sense amplifiers serial addresses received decoded. As result, '922 patent does not teach integrated circuit memory device with power saving its consideration.

Similarly, U.S. Pat. No. 6,097,657 also does not teach activating sensing amplifiers only after all various addresses been completed decoded thereby saving power sensing amplifier.

Accordingly, there need for integrated circuit memory device that rapid that it decodes partially received address serially addressed memory device well saving power operation memory device.

SUMMARY OF THE INVENTION

In present invention integrated circuit memory device comprises array memory cells that are arranged plurality rows columns with plurality row lines plurality column lines. The cells which are arranged same row are connected by common row line cells which are arranged same column are connected by common column line. Each cell array addressed by address signal having plurality bits. An address input receives plurality bits address signal series. A sensing amplifier circuit connectable one or more plurality column lines array. Each column lines connectable pre-charged voltage response read command. Finally, decode circuit receives address signal decodes address signal each plurality bits received disconnects certain column lines pre-charged voltage response decoding activates sense amplifier circuit after all plurality bits address signal are received.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 block level schematic diagram integrated circuit memory device present invention.

FIG. 2 circuit diagram non-volatile memory cell which used integrated circuit memory device which shown FIG. 1.

FIG. 3 circuit diagram another non-volatile memory cell which used integrated circuit memory device shown FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

Referring FIG. 1 there shown block level diagram integrated circuit memory device 10 present invention. The device 10 comprises array 12 memory cells which are arranged plurality rows columns. As well known art, term rows columns used herein, may interchanged. The array 12 further plurality row lines 14 plurality row columns 16 . Memory cells that are arranged same row, e.g. 14 , are connected by common row line 14 . Memory cells which are arranged same column are connected by common column line, such column lines 16 . Each memory cells intersection column line row line addressed by address signal. The address signal received address terminal 20 . In memory device 10 , address signal comprises plurality bits received serial manner. The address signal applied shift register 22 comprising first shift register 22 second shift register 22 b . As well known art, typically address signal two components: first component for row address second component for column address. Thus, first component, row address, stored first shift register 22 second component column address stored second shift register 22 b.

The memory device 10 also comprises row address decoder 24 which receives row address stored first shift register 22 . In response, row address decoder 24 selects or activates one row lines 14 connected array 12 . Each column lines 16 connected through MOS transistor switch 30 pre-charged circuit 32 source voltage such Vcc or another bias voltage. Each column lines 16 also connected multiplexer 34 which connected sense amplifier 36 whose output connected latch 38 .

The memory device 10 also comprises column address decoder 40 which receives second component address signal second shift register 22 b . In response decoding address signal second shift register 22 b , column address decoder 40 controls operations each switches 30 ( a–z ), through inverter 44 , connecting or disconnecting each column lines 16 pre-charged circuit 32 . Finally, memory device 10 comprises control circuit 42 . The control circuit 42 receives externally supplied clock signal externally supplied read command. In response thereto, control circuit 42 controls operation first second shift registers 22 22 b well column address decoder 40 pre-charged circuit 32 . The output column address decoder 40 also used control operation multiplexer 34 activate sense amplifier 36 through logic circuit 46 , such AND gate 46 .

Referring FIG. 2 that shown first embodiment non-volatile single storage transistor stacked gate floating gate type which used array 12 memory device 10 . The operation such stacked gate floating gate storage transistor well known art. Referring FIG. 3 there shown split gate floating gate storage transistor which also used array 12 memory device 10 . Such split gate floating gate storage transistor shown FIG. 3 operated accordance with teaching disclosed U.S. Pat. No. 5,029,130 whose disclosure incorporated herein by reference its entirety. In particular, split gate floating gate storage transistor programmed by hot channel electron injection erased by Fowler-Nordheim tunneling electrons floating gate control gate. For each cells type shown FIG. 2 or 3 , row line connected control gate, column line connected one terminals connected channel cell. Such connections are well known art.

The operation memory device 10 follows. The memory device 10 receives read command by control circuit 42 . In response, control circuit 42 activates pre-charge circuit 32 connecting pre-charged voltage each column lines 16 . As discussed hereinafter, this act pre-charging each column lines 16 may delayed until start decoding column address portion address signal, thereby saving power. Alternatively, discussed herein below, connection each column line(s) 16 pre-charging circuit 32 pre-charging voltage may initiated by first or subsequent bit column address.

The memory device 10 assumed receive address signal having plurality bits which first component row address. In that event, plurality bits first received stored first shift register 22 . When first shift register 22 filled, bits are read out parallel supplied row address decoder 24 which decodes row address signal selects particular row line 14 . The second component address signal, column address, then supplied stored bit by bit into second shift register 22 b . As each bit received by second shift register 22 b , it read out column address decoder 40 decoded. Since first bit column address most significant bit, lieu read command used initiate pre-charging sequence, first bit or subsequent bit (but prior last bit) column address may used connect all column line(s) 16 pre-charging circuit 32 pre-charging voltage. As each subsequent column address bit received decoded, column decoder 40 turns off appropriate switches 30 thereby deselecting or turning off unselected column lines 16 pre-charged voltage. When column address completely received second shift register 22 b , column address decoder 40 would completely decoded column address would deselected or turned off all unselected column lines 16 leaving only selected column line(s) 16 connected pre-charged circuit 32 pre-charged voltage. At that moment, completely decoded column address then used activate multiplexer 34 connect selected column line(s) 16 sense amplifier 36 . At same time, when column address completely decoded, column address decoder 40 also activates sense amplifier 36 turning it on. Since sense amplifier 36 turned least one clock cycle after selected column line(s) 16 been raised pre-charged voltage, there larger differential signal that available that time for sense amplifier 36 detect. The detected state cell connected selected column line(s) 16 sensed by sense amplifier 36 which then stored latch 38 .

As seen foregoing, there are advantages apparatus method present invention. First, by initiating pre-charging all column lines then during pre-charging process, deselecting unselected column lines partial column address received decoded, speed operation increased. Further, by not enabling sense amplifier 36 until final column address signal known, power dissipated by sensing amplifier circuit 36 saved applied only when it needed. Finally, since sense amplifier 36 activated least one clock cycle after bit line(s) or column line(s) are pre-charged, there larger differential signal available that time which increases signal noise ratio, further enhancing speed/power consumption tradeoffs.