Method of determining voltage compensation for flash memory devices

What claimed is:




1. A method characterizing programming properties dual bit flash memory cell comprising: applying drain voltage acting drain memory cell applying source voltage acting source memory cell; concurrently applying gate voltage gate memory cell, wherein gate voltage initial value; measuring drain source current acting drain acting source repeatedly adjusting applied gate voltage according measured drain current until measured drain current about acceptable value; determining gate voltage adjustment for memory cell according final value applied gate voltage initial value; determining drain voltage adjustment for memory cell.


2. The method claim 1, wherein applying source voltage acting source comprises biasing source voltage value selected range comprising −0.5 volts +0.5 volts.


3. The method claim 1, wherein adjusting applied gate voltage comprises increasing applied gate voltage by step value.


4. The method claim 1, wherein adjusting applied gate voltage comprises decreasing applied gate voltage by step value.


5. The method claim 1, wherein initial value about 10 volts.


6. The method claim 1, wherein drain voltage determined according distance bitline contacts.


7. The method claim 1, wherein determining drain voltage adjustment comprises setting drain voltage adjustment equal gate voltage adjustment.


8. The method claim 1, further comprising programming memory cell by applying gate voltage having initial value gate memory cell, by connecting acting source memory cell ground, applying drain voltage drain voltage adjustment acting drain memory cell.


9. The method claim 1, further comprising: determining drain voltage adjustments for additional memory cells within memory device; segmenting memory cell additional memory cells device into number groups according programming properties, wherein programming properties include determined drain voltage adjustments; selecting group drain voltage adjustments for number groups that allow programming memory cells within groups.


10. The method claim 9, wherein segmenting memory cell additional memory cells according programming properties includes segmenting according distances bitline contacts.


11. The method claim 9, wherein segmenting memory cell additional memory cells device according programming properties includes segmenting according distance power source.


12. The method claim 9, wherein selecting group drain voltage adjustments comprises determining average drain voltage adjustment for memory cells within respective groups.

FIELD OF INVENTION

The present invention relates generally memory devices like, particular determining utilizing voltage compensation for programming flash memory devices.

BACKGROUND OF THE INVENTION

Many different types styles memory exist store data for computers similar type systems. For example, random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), read only memory (ROM), programmable read only memory (PROM), electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) flash memory are all presently available accommodate data storage.

Each type memory its own particular advantages disadvantages. For example, DRAM SRAM allow individual bits data erased one time, but such memory loses its data when power removed. EEPROM alternatively easily erased without extra exterior equipment, but reduced data storage density, lower speed, higher cost. EPROM, contrast, less expensive greater density but lacks ease erasability.

Flash memory, become popular type memory because it combines advantages high density low cost EPROM with electrical erasability EEPROM. Flash memory rewritten hold its contents without power, thus nonvolatile. It used portable electronic products, such cell phones, portable computers, voice recorders, etc. well larger electronic systems, such cars, planes, industrial control systems, etc.

Flash memory generally constructed memory cells where, generally, single bits data are stored read respective memory cells. The cells are generally programmed by hot electron injection erased by Fowler-Nordheim tunneling, however other mechanisms programming and/or erasing employed. As with aspects semiconductor industry, there continuing desire scale down device dimensions achieve higher device packing densities semiconductor wafers. Similarly, increased device speed performance are also desired allow more data stored smaller memory devices. Accordingly, there are ongoing efforts to, among other things, increase number memory cells that packed semiconductor wafer.

Individual memory cells are organized into individually addressable units or groups, which are accessed for read, program, or erase operations through address decoding circuitry. The individual memory cells are typically comprised semiconductor structure adapted for storing bit data. For instance, conventional memory cells include stacked gate metal oxide semiconductor (MOS) device, such transistor which binary piece information may retained. The memory device includes appropriate decoding group selection circuitry, well circuitry provide voltages cells being operated on.

The erase, program, read operations are commonly performed by application appropriate voltages certain terminals memory cell. In erase or write operation voltages are applied so cause charge removed or stored memory cell. In read operation, appropriate voltages are applied so cause current flow cell, wherein amount such current indicative value data stored cell. The memory device includes appropriate circuitry sense resulting cell current order determine data stored therein, which then provided data bus terminals device for access by other devices system which memory device employed.

The memory cell generally source, drain, channel formed there between, well stacked gate structure overlying channel. The stacked gate may further include thin gate dielectric layer (sometimes referred tunnel oxide) formed surface P-well. The stacked gate also includes polysilicon floating gate overlying tunnel oxide interpoly dielectric layer overlying floating gate. The interpoly dielectric layer often multilayer insulator such oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching nitride layer. Lastly, polysilicon control gate overlies interpoly dielectric layer.

In NOR configuration, control gate connected wordline associated with row memory cells form sectors such cells. In addition, drain regions cells are connected together by conductive bitline. The channel cell conducts current between source drain accordance with electric field developed channel by stacked gate structure. Respective drain terminals transistors within single column are connected same bitline. In addition, respective flash cells associated with given bitline stacked gate terminals coupled different wordline, while all flash memory cells array generally their source terminals coupled common source terminal. In operation, individual flash cells are addressed via respective bitline wordline using peripheral decoder control circuitry for programming (writing), reading or erasing functions.

By way further detail, single bit stacked gate flash memory cell programmed by suitable mechanism, such hot electron injection. Programming with hot hole injection involves applying relatively high voltage control gate connecting source ground drain predetermined potential above source. When resulting electric field high enough, electrons collect enough energy injected source onto control gate. As result trapped electrons, threshold voltage cell increases. This change threshold voltage (and thereby channel conductance) cell created by trapped electrons what causes cell programmed.

In order erase typical single bit stacked gate flash memory cell, relatively high voltage applied source, control gate held negative potential, while drain allowed float. Under these conditions, strong electric field developed across tunnel oxide between floating gate source. The electrons that are trapped floating gate flow toward cluster portion floating gate overlying source region are extracted floating gate into source region by way Fowler-Nordheim tunneling through tunnel oxide. As electrons are removed floating gate, cell erased.

For read operation, certain voltage bias applied across drain source cell transistor. The drain cell bitline, which may connected drains other cells byte or word group. A source read voltage applied source drain read voltage applied drain. The drain read voltage greater than source read voltage. A read gate voltage then applied gate (e.g., wordline) memory cell transistor that greater than drain read voltage order cause current flow drain source. The read operation gate voltage typically applied level between programmed threshold voltage (V T ) unprogrammed threshold voltage. The resulting current measured, by which determination made data value stored cell.

Another type flash memory dual bit memory, which allows multiple bits stored single cell. In this technology, memory cell essentially split into two identical (mirrored) parts, each which formulated for storing one two independent bits. Each dual bit memory cell, like traditional cell, gate with source drain. However, unlike traditional stacked gate cell which source always connected electrical source drain always connected electrical drain, respective dual bit memory cells connections source drain reversed during operation permit storing two bits.

In virtual ground type architecture, dual bit memory cells semiconductor substrate with implanted conductive bitlines. A multilayer storage layer, referred “charge-trapping dielectric layer”, formed over semiconductor substrate. The charge-trapping dielectric layer generally composed three separate layers: first insulating layer, charge-trapping layer, second insulating layer. Wordlines are formed over charge-trapping dielectric layer substantially perpendicular bitlines. Programming circuitry controls two bits per cell by applying signal wordline, which acts control gate, changing bitline connections such that one bit stored by source drain being connected one arrangement complementary bit stored by source drain being interchanged another arrangement.

Programming flash memory cells sensitive. Programming dual bit memory cells even more sensitive because programming involves applying program voltages control gate, selecting bitline connections according which bit being programmed, applying program voltages acting source drain. Conditions, such path resistance, alter applied program voltages values that are outside acceptable ranges for dual bit memory cells. Such programming failures result problems including loss time result re-programming operations, loss data, like.

SUMMARY OF THE INVENTION

The following presents simplified summary invention order provide basic understanding some aspects invention. This summary not extensive overview invention. It intended neither identify key or critical elements invention nor delineate scope invention. Rather, its primary purpose merely present one or more concepts invention simplified form prelude more detailed description that presented later.

The present invention determines or identifies programming variations for different groups memory cells within array or memory device that adequately program memory cells within respective groups. Then, during programming operations for given memory cell, programming voltages are applied according determined or identified programming variations for group which given memory cell belongs. These adjusted programming variations result relatively better programming, terms successful programs, data integrity, like, than conventional programming methods that employ single set programming voltages for array or device. Additionally, adjusted programming variations yield relatively more uniform threshold voltage distribution. As result, faster erase operations performed, which provides improved endurance characteristics reliability.

For given dual bit flash memory device, portion memory cells device are characterized identify programming variations or adjustments. Subsequently, memory cells are segmented into groups according identified programming variations and, optionally, other properties such location device. During programming particular memory cell, associated group which particular cell member identified programming voltages are obtained associated group. The memory cell programmed with obtained programming voltages with improved programming results, such data integrity, programming success rate, like, compared with conventional programming methods that treat all memory cells device or array identically during programming.

To accomplishment foregoing related ends, following description annexed drawings set forth detail certain illustrative aspects implementations invention. These are indicative but few various ways which one or more aspects present invention may employed. Other aspects, advantages novel features invention become apparent following detailed description invention when considered conjunction with annexed drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 top view dual bit flash memory device accordance with aspect present invention.

FIG. 2 schematic illustration portion memory core such may include least part one cores depicted FIG. 1 virtual ground type configuration accordance with aspect present invention.

FIG. 3 top view least portion memory core, such may include least part one cores depicted FIG. 1 accordance with aspect present invention.

FIG. 4 cross-sectional isometric illustration portion dual bit flash memory, such that taken along line 4 — 4 FIG. 3 accordance with aspect present invention.

FIG. 5A schematic diagram dual bit memory cell during programming first bit accordance with aspect present invention.

FIG. 5B schematic diagram dual bit memory cell during programming second bit accordance with aspect present invention.

FIG. 6 top view illustrating least portion memory core/device, such may include least part one M by N array cores depicted FIG. 1 accordance with aspect present invention.

FIG. 7 flow diagram illustrating method characterizing programming properties dual bit memory cell accordance with aspect present invention.

FIG. 8 flow diagram illustrating method determining drain voltage adjustments for groups similarly characterized memory cells accordance with aspect present invention.

FIG. 9 flow diagram illustrating method programming memory cell accordance with aspect present invention.

DETAILED DESCRIPTION OF THE INVENTION

One or more aspects present invention are described with reference drawings, wherein like reference numerals are generally utilized refer like elements throughout, wherein various structures are not necessarily drawn scale. In following description, for purposes explanation, numerous specific details are set forth order provide thorough understanding one or more aspects present invention. It may evident, however, one skilled art that one or more aspects present invention may practiced with lesser degree these specific details. In other instances, well-known structures devices are shown block diagram form order facilitate describing one or more aspects present invention.

One trend flash memory devices, particularly dual bit flash memory devices, increase array sizes larger larger ever increasing higher densities. As result, amount resistance along conductive lines array one end array another also increases. Accordingly, “ideal” programming conditions, those conditions which result programming memory cells substantially all time, for one group or sector array vary for another group or sector.

The present invention determines or identifies programming variations for different groups within array or memory device that adequately program memory cells within respective groups. Then, during programming operations for given memory cell, programming voltages are applied according determined or identified programming variations for group which given memory cell belongs.

Referring initially FIG. 1, top view exemplary dual bit flash memory 100 accordance with aspect present invention illustrated. The memory 100 generally includes semiconductor substrate 102 which one or more high-density core regions 104 one or more lower-density peripheral portions are formed. The high-density density core regions typically include one or more M by N arrays 104 individually addressable, substantially identical dual bit flash memory cells. The lower-density peripheral portions other hand typically include peripheral control circuitry 106 . The lower-density peripheral portions also include programming circuitry for selectively addressing individual memory cells. The programming circuitry represented part by includes one or more x-decoders 108 one or more y-decoders 110 that cooperate with peripheral control circuitry 106 for selectively connecting source, gate, and/or drain selected addressed memory cells predetermined voltages or impedances effect designated operations respective memory cells (e.g., programming, reading, erasing, deriving necessary voltages effect such operations).

Turning FIG. 2, schematic illustration presented portion 200 exemplary memory core such may include least part one M by N array cores 104 depicted FIG. 1 accordance with aspect present invention. The circuit schematic shows line memory cells, which includes memory cells 201 through 204 virtual ground type implementation, for example. The respective memory cells 201 through 204 are connected wordline 206 , which serves control gate, pairs memory cells share common bitline. For instance, example shown, memory cell 201 associated bitlines 208 209 ; memory cell 202 associated bitlines 209 210 ; memory cell 203 associated bitlines 210 211 ; memory cell 204 associated bitlines 211 212 . As such, cells 201 202 share bitline 209 , cells 202 203 share bitline 210 cells 203 204 share bitline 211 , respectively.

Depending upon signal wordline connection bitlines memory cell electrical source or drain, memory cells 201 through 204 are capable programmed, read, and/or erased locations 215 through 222 . For example, control bit location 215 achieved through connection drain bitline 208 source bitline 209 . Similarly, control bit location 216 achieved through connection drain bitline 209 source bitline 208 . Programming bit location 215 attained through connection drain bitline 209 source bitline 208 programming bit location 216 attained through connection drain bitline 208 source bitline 209 . It appreciated that although adjacent memory cells share common bitlines, adjacent memory cells do not interfere with each other because memory cells are typically read programmed one time such instances only one memory cell active time while reading or programming.

Referring now FIG. 3, top view presented least portion 300 memory core, such may include least part one M by N array cores 104 depicted FIG. 1 accordance with aspect present invention. The memory 300 formed upon semiconductor substrate 102 plurality implanted bitlines 304 extending substantially parallel one another, further includes plurality formed wordlines 302 extending substantially parallel one another substantially right angles plurality implanted bitlines 304 . It appreciated that wordlines 302 bitlines 304 contacts interconnections (not shown) programming circuitry. The x-decoders 108 y-decoders 110 , depicted FIG. 1, pass program gate drain voltages carry out programming functions correct row/column core cell.

FIG. 4 cross-sectional isometric illustration portion 400 dual bit flash memory, such that taken along line 4 — 4 FIG. 3. A semiconductor substrate 102 upon which memory formed doped with p-type impurity such boron, for example, establish threshold adjustment implant (V tadjust ) region 402 therein. The threshold adjustment implant provides region 402 that more heavily doped than semiconductor substrate 102 . The substrate can, for example, formed out silicon itself doped with p-type impurity. The threshold adjustment implant 402 assists controlling threshold voltage various cells within memory 400 .

A charge-trapping dielectric layer 404 deposited over semiconductor substrate 102 . The charge-trapping dielectric layer 404 generally composed three separate layers: first insulating layer 406 , charge-trapping layer 408 , second insulating layer 410 . The first second insulating layers 406 410 are typically formed oxide dielectric such silicon dioxide (SiO 2 ) charge-trapping layer 408 generally formed nitride dielectric such silicon nitride (Si x N y ). The oxide-nitride-oxide configuration commonly referred ONO layer for convenience. Alternatively, other types charge-trapping layers may employed are contemplated falling within scope present invention.

First second conductive bitlines 412 414 are depicted FIG. 4 underlying charge trapping dielectric layer 404 . It appreciated that any number such bitlines implanted into semiconductor substrate 102 , that such bitlines may correspond bitlines 304 depicted FIG. 3. The bitlines are typically formed implanted n-type material, such arsenic, may include oxide portion (not shown) some examples. The first second conductive bitlines 412 414 are spaced apart define channel region 416 there-between.

First second conductive wordlines 418 , 420 are similarly depicted overlying charge-trapping dielectric layer 404 . It appreciated that any number such wordlines formed over dielectric layer 404 , that such wordlines may correspond wordlines 302 depicted FIG. 3. The wordlines formed out polysilicon material, for example, where polysilicon material may deposited over dielectric layer 404 then patterned etched.

FIGS. 5A 5B, described below, illustrate programming dual bit memory cell accordance with present invention. The dual bit memory cell operable store first bit second bit allows programming reading each bit, individually. Typically, erasing performed array or sector blanket operation that erases all cells within array.

FIG. 5A schematic diagram dual bit memory cell 500 during programming first bit accordance with aspect present invention. The memory cell 500 includes gate 501 , first active region 502 , second active region 503 . The first active region 502 second active region 503 operate acting source or drain, depending which bit being programmed or read. To program first bit, first active region 502 acting source second active region acting drain.

Nominal programming values are associated with memory device or array which memory cell 500 part. The nominal values include program gate voltage, program source voltage, program drain voltage. Typically, program source voltage ground, but may differ. Additionally, memory cell 500 member group one or more memory cells that associated programming voltage adjustments for one or more gate 501 , acting source, acting drain. As result, adjustment values including one or more gate adjustment value, drain adjustment value, source adjustment value are present. These values zero, positive, and/or negative. Prior testing characterizing memory cell 500 and/or other cells established these adjustment values.

The memory cell 500 programmed by applying program gate voltage gate adjustment value gate 501 , applying program source source adjustment value acting source 502 , applying program drain drain adjustment value acting drain 503 . As result, programming operation performed with relatively more properly than without adjustment values. The adjustment values compensate for conditions such path resistance that alter applied voltages seen by memory cell 500 .

FIG. 5B schematic diagram dual bit memory cell 500 during programming second bit accordance with aspect present invention. The memory cell 500 includes gate 501 , first active region 502 , second active region 503 . The first active region 502 second active region 503 operate acting source or drain, depending which bit being programmed or read. To program second bit, first active region 502 acting drain second active region acting source.

Nominal programming values are associated with memory device or array which memory cell 500 part. The nominal values include program gate voltage, program source voltage, program drain voltage. Typically, program source voltage ground. Additionally, memory cell 500 member group one or more memory cells that associated programming voltage adjustments for one or more gate 501 , acting source, acting drain. As result, adjustment values including one or more gate adjustment value, drain adjustment value, source adjustment value are present. These adjustment values zero, positive, and/or negative. Prior testing characterizing memory cell 500 and/or other cells established these adjustment values.

The memory cell 500 programmed by applying program gate voltage gate adjustment value gate 501 , applying program source source adjustment value acting source 503 , applying program drain drain adjustment value acting drain 502 . As result, programming operation performed with relatively more properly than without adjustment values. The adjustment values compensate for conditions such path resistance that alter applied voltages seen by memory cell 500 .

FIG. 6 top view illustrating least portion 600 memory core/device, such may include least part one M by N array cores 104 depicted FIG. 1 accordance with aspect present invention. This view exemplary nature provided illustrate grouping memory cells that similar programming characteristics accordance with present invention. The memory portion 600 formed upon semiconductor substrate 601 plurality implanted bitlines 604 extending substantially parallel one another, further includes plurality formed wordlines 602 extending substantially parallel one another substantially right angles plurality implanted bitlines 604 . The view includes first bitline contact 606 second bitline contact 608 . It appreciated that wordlines 302 bitlines 304 other contacts interconnections (not shown) programming circuitry such may represented, least part, by x-decoders 108 y-decoders 110 depicted FIG. 1.

Flash memory devices are typically fabricated with bitline contacts for given bitline that are repeatably present every so memory cells. Bitline contacts could formed for every memory cell memory device, but doing so would lead excessive amount area consumption. Alternatively, single contact could employed per bitline, however path resistance present bitlines would result substantial variations applied voltages for memory cells along bitlines due resistance contact memory cell. This contact memory cell resistance reduces voltages seen memory cells that applied contact.

The present invention employs placing bitline contacts along bitlines selected intervals thereby mitigating contact memory cell resistance mitigating area usage. For example, FIG. 6 shows interval 12 wordlines, however other suitable intervals including 8, 16, like, employed accordance with present invention.

Basic diffraction pattern physics used manufacturing integrated circuits suggest that memory cells close edge sector and/or contact behave differently than those further away. This tends repeating pattern within group transistors (e.g., array, sector, like). As result, group memory cells segmented into groups or subgroups memory cells that similar programming and/or operational properties. Programming variations then determined for groups memory cells that similar programming properties employed during programming more efficiently accurately program memory cells.

Referring again FIG. 6, there are 12 wordlines (WL 0 WL 11 ) 602 within memory portion 600 memory device. Memory cells wordlines WL 0 WL 11 are first second bitline contacts ( 606 608 ). Through characterization and/or analysis, memory cells memory portion 600 grouped into groups having similar programming properties. One suitable, exemplary grouping/subgrouping first group memory cells WL 0 WL 11 , second group memory cells WL 1 WL 10 , third group memory cells WL 2 WL 9 , fourth group memory cells WL 3 WL 8 , fifth group memory cells WL 4 WL 7 , sixth group memory cells WL 5 WL 6 . The above groups trait being substantially similar distances first contact 606 or second contact 608 .

Because present invention provides for adjusted programming values for different memory cells and/or groups memory cells, memory devices supported having relatively larger intervals for bitline contacts than memory devices that do not provide for adjusted programming values.

In view foregoing structural functional features described supra, methodologies accordance with various aspects present invention better appreciated with reference FIGS. 1 6. While, for purposes simplicity explanation, methodologies FIGS. 7, 8 , 9 are depicted described executing serially, it understood appreciated that present invention not limited by illustrated order, some aspects could, accordance with present invention, occur different orders and/or concurrently with other aspects that depicted described herein. Moreover, not all illustrated features may required implement methodology accordance with aspect present invention.

FIG. 7 flow diagram illustrating method 700 characterizing programming properties dual bit memory cell accordance with aspect present invention. The method 700 operates first bit memory cell applies variety voltages memory cell order determine programming adjustments specific memory cell.

The method 700 begins block 702 wherein predetermined drain voltage applied acting drain memory cell. The acting drain active region or bitline associated with first bit memory cell. A gate voltage applied gate memory cell block 704 . The initial gate voltage positive value, such as, for example, about 9 volts. An acting source associated with first bit memory cell biased about ground or voltage about zero block 706 .

Continuing block 708 , drain source current measured gate voltage adjusted (e.g., incremented or decremented) according measured drain source current until measured drain source current acceptable value. The adjusted gate voltage that obtained acceptable measured drain source current, referred measured gate voltage, initial gate voltage are compared determine gate voltage adjustment block 710 . The acceptable measured drain source current vary technology technology, but should generally or about expected programming current per bit, address, word, page, pages, sector, or like depending how programming current defined. The gate voltage adjustment positive or negative, such as, for example, +/−0.1 volts.

The device physics flash memory devices, especially dimensions become smaller smaller, suggest that measured programming adjustment substantially due biasing acting source being non zero level. As result, amount compensation for program drain voltage about same order gate voltage adjustment determined above. Accordingly, drain voltage adjustment value for programming determined block 712 . The drain voltage adjustment value same order magnitude gate voltage adjustment, but not necessarily equal gate voltage adjustment. The gate voltage adjustment typically function where sector laid out device, wherein sectors further away origin gate voltage supply require larger adjustments sectors closer origin gate voltage supply require smaller adjustments. The drain voltage adjustment generally function wordline symmetry, wherein groups or sets memory cells farther away bitline contacts typically, but not always, require greater adjustment due more resistive path. The drain voltage adjustment determined by characterizing memory cell (e.g., via test chip or test product vehicle) analyzing resulting data.

FIG. 8 flow diagram illustrating method 800 determining drain voltage adjustments for groups similarly characterized memory cells accordance with aspect present invention. The method 800 operates memory cells within array or device order characterize group memory cells with similar programming characteristics. Then, method 800 selects programming characteristics for created groups.

The method 800 begins block 802 where gate voltage adjustments for least portion memory cells memory device. The memory device entire core area, array, one or more sectors, like. The method 700 FIG. 7 above employed obtain gate voltage adjustments. The portion or memory cells characterized are selected simulate similarly situated memory cells within device, thereby avoiding determining gate voltage adjustments for all memory cells device. However, it appreciated that present invention includes determining gate voltage adjustments for all or some memory cells particular memory device. Alternately, gate voltage adjustments determined function location or distance gate voltage supply instead method 700 FIG. 7.

The method 800 continues block 804 wherein drain voltage adjustments are determined for portion memory cells. As stated above, device physics flash memory devices suggest that measured programming adjustment substantially due biasing acting source being non zero level. An amount compensation for program drain voltage about same order gate voltage adjustment determined above. The drain voltage adjustment generally function wordline symmetry, wherein groups or sets memory cells farther away bitline contacts typically, but not always, require greater adjustment due more resistive path. The drain voltage adjustment determined by characterizing memory cell (e.g., via test chip or test product vehicle) analyzing resulting data. Some examples suitable drain voltage adjustments gate voltage adjustments include −0.5 +0.5, −1.0 +0.5, like. However, present invention not limited specific range drain and/or gate voltage adjustments, which vary according characteristics various memory devices, includes other suitable ranges drain and/or gate voltage adjustments.

Memory cells device are segmented or defined into number groups memory cells block 806 , wherein groups similar properties including, but not limited to, similar drain voltage adjustments, similar distance contacts, similar distance power source, like. FIG. 6, described above, illustrates exemplary grouping memory cells accordance with present invention. Thus, grouping based determined or expected drain voltage adjustments, range distances contacts, sector location, and/or combinations thereof.

Subsequently, drain voltage adjustments are selected for number groups block 808 . Additionally, gate and/or source voltage adjustments also selected for number groups. The group drain voltage adjustments are selected such that adjustment permits programming all memory cells within respective group. One suitable mechanism for selecting drain voltage adjustment for given group derive average drain voltage adjustment for memory cells group.

It appreciated that alternate aspects invention include deriving adjustments for groups addition or instead drain voltage adjustments based source voltage adjustments and/or gate voltage adjustments.

FIG. 9 flow diagram illustrating method 900 programming memory cell accordance with aspect present invention. The method 900 operable program bit memory cell employs programming voltages tailored for memory cell order improve programming cell.

The method 900 begins block 902 where group identified that memory cell belongs to. The group group one or more memory cells that similar or substantially similar programming characteristics including, but not limited to, program gate voltage, program drain voltage, program source voltage. The identified group one number groups memory cells for memory device or memory array.

Program voltages, including program gate voltage, program drain voltage, program source voltage, associated with identified group are obtained block 904 . The program voltages are based nominal values for entire device or array adjustment value specific group which memory cell member. One or more voltages vary nominal values. Characterization grouping operations are performed previously identify adjustments appropriately group memory sells. FIGS. 7 8 illustrate suitable characterization grouping operations accordance with present invention.

The memory cell then programmed block 906 with program drain voltage, program source voltage, program drain voltage obtained for identified group. The program drain voltage applied acting drain memory cell, program source voltage, typically ground, applied acting source memory cell, program gate voltage applied gate memory cell. Subsequently, program operation verified block 908 ensure that memory cell indeed programmed. If verification fails, memory cell reprogrammed again until successful verification.

Although invention been shown described with respect one or more implementations, equivalent alterations modifications occur others skilled art based upon reading understanding this specification annexed drawings. The invention includes all such modifications alterations limited only by scope following claims. In particular regard various functions performed by above described components (assemblies, devices, circuits, etc.), terms (including reference “means”) used describe such components are intended correspond, unless otherwise indicated, any component which performs specified function described component (i.e., that functionally equivalent), even though not structurally equivalent disclosed structure which performs function herein illustrated exemplary implementations invention. In addition, while particular feature invention may been disclosed with respect only one several implementations, such feature may combined with one or more other features other implementations may desired advantageous for any given or particular application. Furthermore, extent that terms “includes”, “having”, “has”, “with”, or variants thereof are used either detailed description or claims, such terms are intended inclusive manner similar term “comprising.”