Comprehensive erase verification for non-volatile memory

What claimed is:




1. A method erasing non-volatile memory, comprising: erasing group non-volatile storage elements during user operation; performing erase verification operation determine if said group non-volatile storage elements erased, said performing determines whether there first current flow above first minimum current level first direction through said group; reading said group non-volatile storage elements for erased state, said reading determines whether there second current flow above second minimum current level second direction through said group; verifying that said group erased if said erase verification operation determines that said group erased said step reading reads said group erased.


2. A method according claim 1, wherein: said step reading includes simultaneously reading each storage element said group for erased state.


3. A method according claim 2, wherein simultaneously reading each storage element said plurality comprises: applying first voltage control gate each storage element said group; determining whether said second current flow through said group with said first voltage applied above said second minimum current level.


4. A method according claim 3, wherein: said step reading reads said group erased if said second current flow above said first second minimum current level.


5. A method according claim 1, wherein: said first minimum current level said second minimum current level are equal.


6. The method claim 1, wherein: said step performing erase verification operation determines whether there first current flow above first minimum current level by determining whether charge portion said group above minimum voltage level.


7. A method according claim 1, wherein: said reading determines whether said second current flow through said group above said second minimum current level by determining whether charge portion said group below minimum voltage level.


8. A method according claim 1, further comprising: marking said group defective if said step performing erase verification operation determines that said group erased said step reading does not read said last one storage element erased.


9. A method according claim 1, wherein: said step performing erase verification operation includes applying first set bias conditions said group; said step reading includes applying second set bias conditions said group.


10. A method according claim 9, wherein: said step performing erase verification operation includes determining whether charge first portion said group above minimum level when said first set bias conditions applied; said step reading includes determining whether charge second portion said group below maximum level when said second set bias conditions applied.


11. A method according claim 9, wherein: said step performing erase verification operation determines that said group erased if said charge said first portion above said minimum level; said step reading reads said least one storage element erased if said charge said second portion below said maximum level.


12. A method according claim 9, wherein: said step determining whether charge first portion said group above minimum level determines whether said charge above said minimum level after period time after applying said first set bias conditions; said step determining whether charge second portion said group below maximum level determines whether said charge below said maximum level after period time after applying said second set bias conditions.


13. A method according claim 9, wherein: said first portion said second portion are same portion.


14. A method according claim 13, wherein: said group NAND string; said NAND string includes source side drain side, said drain side coupled bit line; said same portion said drain side.


15. A method according claim 14, wherein: said NAND string includes select gate; said step applying said first set bias conditions causes current flow said source side said drain side when said string erased; said step applying said second set bias conditions causes current flow said drain side said source side when said string erased said select gate not defective.


16. The method claim 15, wherein: said select gate coupled said drain side said string.


17. The method claim 15, wherein: said select gate coupled said source side said string.


18. A method according claim 9, wherein said step applying first set bias conditions includes: applying first voltage each storage element said group, said first voltage sufficient turn erased storage element; applying second voltage source side said group; applying third voltage drain side said group, said third voltage less than said second voltage.


19. A method according claim 9, wherein said step applying second set bias conditions includes: applying first voltage each storage element said group, said first voltage sufficient turn erased storage element; applying second voltage source side said group; applying third voltage drain side said group, said third voltage greater than said second voltage.


20. A method according claim 19, wherein: said first voltage not sufficient turn programmed storage element.


21. A method according claim 1, wherein: said group part block storage elements; said method further comprises marking said block defective if said step performing erase verification operation determines that said group erased said step reading does not read said least one storage element erased.


22. A method according claim 1, wherein: said group non-volatile storage elements are binary storage elements.


23. A method according claim 1, wherein: said group non-volatile storage elements are multi-state storage elements.


24. A method according claim 1, wherein: said group non-volatile storage elements are flash storage elements.


25. A method according claim 1, wherein: said group storage elements part array storage elements; said array storage elements communication with host system; said array storage elements removable said host system.


26. A method according claim 1, further comprising: enabling program operation said group if said step performing erase verification operation determines that said group erased said step reading reads said least one storage element erased.


27. A method according claim 8, wherein: said step marking said group defective includes mapping said group another group non-volatile storage elements.


28. A method according claim 2, wherein: said step simultaneously reading each storage element comprises performing NAND string read operation.


29. A method according claim 1, wherein: said group non-volatile storage elements are part memory system; said steps performing erase verification operation reading said group are performed by controller; said controller part said memory system.


30. A memory system, comprising: group non-volatile storage elements located host system, said group includes source side drain side; managing circuit communication with said group, said managing circuit causes erase operation performed for said group, said managing circuit performs erase verification operation determine whether said group erased reads least one non-volatile storage element said group for erased state after erasing said group, said managing circuit reads said least one non-volatile storage element for erased state by applying first voltage sufficient turn erased storage element each non-volatile storage element said group, applying second voltage said source side, applying third voltage said drain side, said third voltage greater than said second voltage, wherein said managing circuit verifies that said group erased when said erase verification operation determines that said group erased said least one non-volatile storage element read erased.


31. A memory system according claim 30, wherein: said group non-volatile storage elements are connected series.


32. A memory system according claim 30, wherein: said group NAND string.


33. A memory system according claim 30, wherein: said managing circuit simultaneously reads each storage element said group for erased state, wherein said managing circuit applies said first voltage each storage element said group determines whether current flow through said group with said first voltage applied above minimum current level simultaneously read each storage element.


34. A memory system according claim 30, wherein: said group non-volatile storage elements are multi-state NAND flash memory devices.


35. A memory system according claim 30, wherein: said memory system further comprises array storage elements; said group part said array; said array removable said host system.


36. A memory system according claim 30, wherein: said managing circuit includes least one controller state machine.


37. A memory system according claim 30, wherein: said managing circuit performs said erase verification operation reads least one storage element during user operation said memory system.


38. A method operating non-volatile memory, comprising: performing plurality programming operations store user data memory system; performing plurality erase operations erase said user data, wherein least one said erase operations includes steps of: erasing group non-volatile storage elements said memory system; performing erase verification operation determine whether said group erased after said step erasing, said performing includes determining whether charge first portion said group above minimum level, reading least one non-volatile storage element said group for erased state, said reading includes determining whether charge second portion said group below maximum level, verifying that said group erased if said step performing erase verification operation determines that said group erased said step reading reads said last one storage element erased.


39. A method according claim 38, wherein: said step reading includes reading said group for erased state, wherein reading said group includes simultaneously reading each storage element said group by applying set bias conditions said group testing conduction first direction through said group.


40. A method according claim 39, wherein: said step performing erase verification operation tests conduction second direction through said group.


41. A method according claim 38, wherein: said group non-volatile storage elements are multi-state flash storage elements.


42. A method according claim 38, wherein: said group part array storage elements; said array communication with host system; said array removable said host system.


43. A method according claim 38, wherein: said group non-volatile storage elements are part memory system; said step performing plurality erase operations performed by controller; said controller part said memory system.


44. A method erasing non-volatile memory, comprising: erasing group non-volatile storage elements during user operation; performing erase verification operation determine if said group non-volatile storage elements erased; reading said group non-volatile storage elements for erased state, said reading includes applying first voltage sufficient turn erased storage element each non-volatile storage element said group, applying second voltage source side said group, applying third voltage drain side said group, said third voltage greater than said second voltage; verifying that said group erased if said erase verification operation determines that said group erased said step reading reads said group erased.


45. A method according claim 44, wherein: said performing erase verification operation determines whether there first current flow above first minimum current level first direction through said group.


46. A method according claim 45, wherein: said reading said group determines whether there second current flow above second minimum current level second direction through said group.


47. A method according claim 46, wherein: said performing erase verification operation determines whether there first current flow above first minimum current level by determining whether charge first portion said group above minimum voltage level; said reading said group determines whether there second current flow above second minimum current level by determining whether charge second portion said group below maximum voltage level.


48. A method according claim 47, wherein: said first portion said second portion are same portion; said minimum voltage level said maximum voltage level are equal.


49. A method according claim 44, wherein: said performing erase verification operation includes applying first set bias conditions said group; said reading said group includes applying second set bias conditions said group.


50. A non-volatile memory system, comprising: group non-volatile storage elements located host system; managing circuit communication with said group, said managing circuit causes erase operation performed for said group, said managing circuit performs erase verification operation determine whether said group erased reads least one non-volatile storage element said group for erased state after erasing said group, said managing circuit reads said least one non-volatile storage element by testing conduction first direction through said group performs said erase verification operation by testing conduction second direction through said group, said managing circuit verifies that said group erased when said erase verification operation determines that said group erased said least one non-volatile storage element read erased.


51. A method according claim 50, wherein: testing conduction first direction includes determining whether charge first portion said group below maximum level while applying first set bias conditions said group; testing conduction second direction includes determining whether charge second portion said group above minimum level while applying second set bias conditions said group.


52. A method according claim 51, wherein: said first portion said second portion are same portion.


53. A method according claim 51, wherein applying said first set bias conditions includes: applying first voltage each storage element said group, said first voltage sufficient turn erased storage element; applying second voltage source side said group; applying third voltage drain side said group, said third voltage greater than said second voltage.


54. A method according claim 51, wherein applying said second set bias conditions includes: applying first voltage each storage element said group, said first voltage sufficient turn erased storage element; applying second voltage source side said group; applying third voltage drain side said group, said third voltage less than said second voltage.


55. A method operating non-volatile memory, comprising: performing plurality programming operations store user data memory system; performing plurality erase operations erase said user data, wherein least one said erase operations includes steps of: erasing group non-volatile storage elements said memory system; performing erase verification operation determine whether said group erased after said step erasing, said erase verification operation tests conduction first direction through said group, reading least one non-volatile storage element said group for erased state, said reading tests conduction second direction through said group, verifying that said group erased if said step performing erase verification operation determines that said group erased said step reading reads said last one storage element erased.


56. A method according claim 55, wherein: testing conduction first direction includes determining whether first current flow through said group above first minimum current level while applying first set bias conditions; testing conduction second direction includes determining whether second current flow through said group above second minimum current level while applying second set bias conditions said group.


57. A method according claim 56, wherein: said first minimum current level said second minimum current level are equal.


58. A method according claim 56, wherein applying said first set bias conditions includes: applying first voltage each storage element said group, said first voltage sufficient turn erased storage element; applying second voltage source side said group; applying third voltage drain side said group, said third voltage less than said second voltage.


59. A method according claim 56, wherein applying said second set bias conditions includes: applying first voltage each storage element said group, said first voltage sufficient turn erased storage element; applying second voltage source side said group; applying third voltage drain side said group, said third voltage greater than said second voltage.

BACKGROUND OF THE INVENTION

1. Field Invention

The present invention relates generally technology for programming non-volatile memory devices.

2. Description Related Art

Semiconductor memory devices become more popular for use various electronic devices. For example, non-volatile semiconductor memory used cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) flash memory are among most popular non-volatile semiconductor memories.

One example flash memory system uses NAND structure, which includes arranging multiple transistors series, sandwiched between two select gates. The transistors series select gates are referred NAND string. FIG. 1 top view showing one NAND string. FIG. 2 equivalent circuit thereof. The NAND string depicted FIGS. 1 2 includes four transistors 100 , 102 , 104 106 series sandwiched between first select gate 120 second select gate 122 . Select gate 120 connects NAND string bit line 126 . Select gate 122 connects NAND string source line 128 . Select gate 120 controlled by applying appropriate voltages control gate 120 CG for select gate 120 . Select gate 122 controlled by applying appropriate voltages control gate 122 CG select gate 122 . Each transistors 100 , 102 , 104 106 includes control gate floating gate. For example, transistor 100 control gate 100 CG floating gate 100 FG. Transistor 102 includes control gate 102 CG floating gate 102 FG. Transistor 104 includes control gate 104 CG floating gate 104 FG. Transistor 106 includes control gate 106 CG floating gate 106 FG. Control gate 100 CG connected word line WL 3 , control gate 102 CG connected word line WL 2 , control gate 104 CG connected word line WL 1 , control gate 106 CG connected word line WL 0 .

Note that although FIGS. 1 2 show four memory cells NAND string, use four transistors only provided example. A NAND string less than four memory cells or more than four memory cells. For example, some NAND strings include eight memory cells, 16 memory cells, 32 memory cells, etc. The discussion herein not limited any particular number memory cells NAND string.

A typical architecture for flash memory system using NAND structure include several NAND strings. For example, FIG. 3 shows three NAND strings 202 , 204 206 memory array having more NAND strings. Each NAND strings FIG. 3 includes two select transistors four memory cells. For example, NAND string 202 includes select transistors 220 230 , memory cells 222 , 224 , 226 228 . NAND string 204 includes select transistors 240 250 , memory cells 242 , 244 , 246 248 . Each string connected source line by its select transistor (e.g. select transistor 230 select transistor 250 ). A selection line SGS used control source side select gates. The various NAND strings are connected respective bit lines by select transistors 220 , 240 , etc., which are controlled by select line SGD. In other embodiments, select lines do not necessarily need common. Word line WL 3 connected control gates for memory cell 222 memory cell 242 . Word line WL 2 connected control gates for memory cell 224 memory cell 244 . Word line WL 1 connected control gates for memory cell 226 memory cell 246 . Word line WL 0 connected control gates for memory cell 228 memory cell 248 . As seen, each bit line respective NAND string comprise columns array memory cells. The word lines (WL 3 , WL 2 , WL 1 WL 0 ) comprise rows array. Each word line connects control gates each memory cell row. For example, word line WL 2 connected control gates for memory cells 224 , 244 252 .

Each memory cell store data (analog or digital). When storing one bit digital data, range possible threshold voltages memory cell divided into two ranges which are assigned logical data “1” “0.” In one example NAND type flash memory, voltage threshold negative after memory cell erased, defined logic “1.” The threshold voltage after program operation positive defined logic “0.” When threshold voltage negative read attempted by applying 0 volts control gate, memory cell turn indicate logic one being stored. When threshold voltage positive read operation attempted by applying 0 volts control gate, memory cell not turn on, which indicates that logic zero stored. A memory cell also store multiple levels information, for example, multiple bits digital data. In case storing multiple levels data, range possible threshold voltages divided into number levels data. For example, if four levels information are stored, there four threshold voltage ranges assigned data values “11”, “10”, “00”, “01.” In one example NAND type memory, threshold voltage after erase operation negative defined “11”. Positive threshold voltages are used for states “10”, “00”, “01.”

Typically, block or other unit memory cells erased prior programming memory cells one or more threshold voltage levels well response request erase portion memory. In one embodiment, block or sector refer minimum number memory cells that are simultaneously erased. An entire memory device or one or more blocks erased during operation device.

Relevant examples NAND type flash memories their operation are provided following U.S. Patents/Patent Applications, all which are incorporated herein by reference: U.S. Pat. No. 5,570,315; U.S. Pat. No. 5,774,397, U.S. Pat. No. 6,046,935, U.S. Pat. No. 6,456,528 U.S. Pat. Application. Ser. No. 09/893,277 (Publication No. U.S. 2003/0002348). Other types flash memory devices also used accordance with embodiments present invention. For example, following patents describe NOR type flash memories are incorporated herein by reference their entirety: U.S. Pat. Nos. 5,095,344; 5,172,338; 5,890,192 6,151,248. Another example flash memory type found U.S. Pat. No. 6,151,248, incorporated herein by reference its entirety.

During manufacturing, it possible that some flash memory devices or portions thereof become defective. Individual transistors, strings, or blocks storage elements may defective unusable. Additionally, defects device may arise after manufacturing process or during user operation. Defects effectively managed most situations by using error correction codes (ECC) or simply not using defective portions device. Individual cells, strings, or blocks mapped alternate areas memory device, such predesignated alternate strings end block. If left undetected, however, defects cause erroneous erase verification some cases, irretrievable user data. Accordingly, various techniques are employed detect accommodate defects flash memory devices.

Defects flash memory discovered during programming erasing flash memory. Groups cells having defective storage elements or select gates not program or erase properly, indicating problem with one or more devices string. During manufacturing, defects flash memory may discovered during number routine testing operations that are performed part manufacturing process. For example, portions device may erased then verified for erased condition. Those cells that fail number erase attempts may determined defective handled under one or more defect management schemes.

The manufacturing process also typically includes reading each cell determine if it functioning properly. For example, after erasing group cells or programming random pattern group, each individual cells group are individually read. If state cell does not match value for which it was programmed, it determined defective.

During user operation, defects detected by cells, strings, or blocks that fail erase or program properly. For example, if cell fails erase after number attempts, cell determined defective. Similarly, if cell fails program desired state after number attempts, it determined defective. During manufacturing user operation, erase verification typically performed by testing group cells single step.

Although these techniques discover some defects memory device verify erasure extent, they may not fully verify that cells are erased detect all defects device.

Accordingly, there need for improved system method verify erase operations detect defects non-volatile memory.

SUMMARY OF THE INVENTION

The present invention, roughly described, pertains technology for detecting defects non-volatile memory. Systems methods accordance with various embodiments verify results erase operations using plurality test conditions better detect defective and/or insufficiently erased storage elements group.

In one embodiment, group storage elements erased tested determine if elements are erased state result erase process. An initial erase verify process may performed group cells after applying erase pulse or voltage group. In erase verification process NAND string, for example, elements are biased turn if erased charging or conduction through NAND string first direction determined. If conduction or charging above minimum level, group passes initial erase verification. Further pulsing verifying performed until group erased or until predetermined number attempts are made. In one embodiment, storage elements that do not successfully pass erase verification process are mapped other sectors memory device.

In one embodiment, group storage elements also read for erased state after being erased. In read for erased state process, one or more storage elements group read determine their respective state. In one embodiment, each storage element group biased turn if erased charging or conduction through group second direction determined. If charging or conduction above minimum level, string read erased. In one embodiment, each cell NAND string simultaneously read for erased state minimize time for performing additional process.

In one embodiment, erase verification process read for erased state process test conduction or charging through group storage elements opposite directions. For example, erase verification process, bit line NAND string monitored determine if it charges predetermined level with each storage element biased turn if erased bit source lines biased first direction. If bit line charges predetermined level, string verified being erased. During read for erased state, bit line monitored determine if it discharges below predetermined level with each storage element biased turn if erased bit source lines biased second direction. If bit line discharges below predetermined level, string read erased. In this manner, entire NAND string simultaneously read for erased state.

In accordance with one embodiment, group storage elements only verified erased state if it passes erase verification process read for erased state. Those groups storage elements that pass erase verification process but are read programmed are determined defective. They excluded further programming operations using one or more defect handling techniques such mapping defective group another group.

In accordance with one embodiment, groups storage elements are read for erased state only when they pass erase verification process. Those cells that fail erase verification process do not undergo further testing such read for erased state process. Accordingly, time costs incurred by implementing extra read for erased state process are minimized.

In one embodiment, system accordance with embodiment present invention include array storage elements managing circuit. The managing circuit include dedicated hardware and/or include hardware that programmed by software stored one or more storage devices such non-volatile memory (e.g. flash memory, EEPROM, etc.) or other memory devices. In one embodiment, managing circuit includes controller state machine. In another embodiment, managing circuit only includes state machine not controller. The managing circuit perform steps discussed above with respect various embodiments. Methods accordance with some embodiments are performed by state machine. In some implementations, state machine same integrated circuit chip array storage elements.

Other features, aspects, objects invention obtained review specification, figures, claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 top view NAND string.

FIG. 2 equivalent circuit diagram NAND string depicted FIG. 1.

FIG. 3 circuit diagram depicting three NAND strings.

FIG. 4 block diagram one embodiment non-volatile memory system which various aspects present invention implemented.

FIG. 5 illustrates exemplary organization memory array.

FIG. 6 table various bias conditions that used accordance with various embodiments.

FIG. 7 cross-sectional view NAND string such that depicted FIG. 1.

FIG. 8 flowchart for erasing storage elements during user operation accordance with one embodiment.

FIG. 9 flowchart for performing erase verification operation accordance with one embodiment.

FIG. 10 flowchart for reading group memory cells for erased state accordance with one embodiment.

DETAILED DESCRIPTION

The invention illustrated by way example not by way limitation figures accompanying drawings which like references indicate similar elements. It should noted that references or one embodiment this disclosure are not necessarily same embodiment, such references mean least one.

In following description, various aspects present invention described. However, it apparent those skilled art that present invention may practiced with only some or all aspects present disclosure. For purposes explanation, specific numbers, materials, configurations are set forth order provide thorough understanding present invention. However, it apparent one skilled art that present invention may practiced without specific details. In other instances, well-known features are omitted or simplified order not obscure present invention.

Various operations described multiple discrete steps turn, manner that most helpful understanding present invention, however, order description should not construed imply that these operations are necessarily order dependent.

FIG. 4 block diagram one embodiment flash memory system that used implement present invention. Memory cell array 302 controlled by column control circuit 304 , row control circuit 306 , c-source control circuit 310 p-well control circuit 308 . Column control circuit 304 connected bit lines memory cell array 302 for reading data stored memory cells, for determining state memory cells during program operation, for controlling potential levels bit lines promote or inhibit programming erasing. Row control circuit 306 connected word lines select one word lines, apply read voltages, apply program voltages combined with bit line potential levels controlled by column control circuit 304 , apply erase voltage. C-source control circuit 310 controls common source line (labeled “C-source” FIG. 5) connected memory cells. P-well control circuit 308 controls p-well voltage.

The data stored memory cells are read out by column control circuit 304 are output external I/O lines via data input/output buffer 312 . Program data stored memory cells are input data input/output buffer 312 via external I/O lines, transferred column control circuit 304 . The external I/O lines are connected controller 318 .

Command data for controlling flash memory device are input controller 318 . The command data informs flash memory what operation requested. The input command transferred state machine 316 that controls column control circuit 304 , row control circuit 306 , c-source control 310 , p-well control circuit 308 data input/output buffer 312 . State machine 316 also output status data flash memory such READY/BUSY or PASS/FAIL.

Controller 318 connected or connectable with host system such personal computer, digital camera, or personal digital assistant, etc. It communicates with host that initiates commands, such store or read data or memory array 302 , provides or receives such data. Controller 318 converts such commands into command signals that interpreted executed by command circuits 314 , which communication with state machine 316 . Controller 318 typically contains buffer memory for user data being written or read memory array.

One exemplary memory system comprises one integrated circuit that includes controller 318 , one or more integrated circuit chips that each contain memory array associated control, input/output state machine circuits. There trend integrate memory arrays controller circuits system together one or more integrated circuit chips. The memory system may embedded part host system, or may included memory card (or other package) that removably inserted into host systems. Such card may include entire memory system (e.g. including controller) or just memory array(s) with associated peripheral circuits (with Controller or control function being embedded host). Thus, controller embedded host or included within removable memory system.

With reference FIG. 5, exemplary structure memory cell array 302 described. As one example, NAND flash EEPROM described that partitioned into 1,024 blocks. The data stored each block simultaneously erased. In one embodiment, block minimum unit cells that are simultaneously erased. In each block, this example, there are 8,512 columns that are divided into even columns odd columns. The bit lines are also divided into even bit lines (BLe) odd bit lines (BLo). FIG. 5 shows four memory cells connected series form NAND string. Although four cells are shown included each NAND string, more or less than four used, for example 16, 32, or another number. One terminal NAND string connected corresponding bit line via first select transistor SGD, another terminal connected c-source via second select transistor SGS.

During read programming operations one embodiment, 4,256 memory cells are simultaneously selected. The memory cells selected same word line (e.g. WL 2 -i), same kind bit line (e.g. even bit lines). Therefore, 532 bytes data read or programmed simultaneously. These 532 bytes data that are simultaneously read or programmed form logical page. Therefore, this example, one block store least eight pages. When each memory cell stores two bits data (e.g. multi-level cell), one block stores 16 pages.

With reference FIG. 5, for example, read verify operations, select gates (SGD SGS) unselected word lines (e.g., WL 0 , WL 1 WL 3 ) are raised read pass voltage (e.g. 4.5 volts) make transistors operate pass gates. The selected word line (e.g. WL 2 ) connected voltage, level which specified for each read verify operation order determine whether threshold voltage concerned memory cell reached such level. For example, read operation one bit memory cell, selected word line WL 2 grounded, so that it detected whether threshold voltage higher than 0V. In verify operation one bit memory cell, selected word line WL 2 connected 2.4V, for example, so that it verified whether threshold voltage reached 2.4V or another threshold level. The source p-well (e.g., p-well 140 depicted FIG. 7) are zero volts. The selected bit lines (BLe) are pre-charged level of, for example, 0.7V. If threshold voltage higher than read or verify level, potential level concerned bit line (BLe) maintains high level, because non-conductive memory cell. On other hand, if threshold voltage lower than read or verify level, potential level concerned bit line (BLe) decreases low level, for example less than 0.5V, because conductive memory cell (e.g., memory cell 303 ). The state memory cell detected by sense amplifier that connected bit line. The difference between whether memory cell erased or programmed depends whether or not negative charge stored floating gate. For example, if negative charge stored floating gate, threshold voltage becomes higher transistor enhancement mode.

Memory cells are erased one embodiment by raising p-well erase voltage (e.g. 20 volts) grounding word lines selected block while source bit lines are floating. Due capacitive coupling, unselected word lines, bit lines, select lines, c-source are also raised high positive potential, (e.g., 20V). A strong electric field thus applied tunnel oxide layers memory cells selected block data selected memory cells are erased electrons floating gates are emitted substrate. As sufficient electrons are transferred floating gate p-well region, threshold voltage selected cell becomes negative. Erasing performed entire memory array, separate blocks, or another unit cells.

The erase, read verify operations described above are performed according techniques known art. Thus, details explained varied by one skilled art.

During user operation, blocks memory cells generally undergo erase verification operation subsequent being erased. An erase verification operation performed insure that all selected cells were successfully erased result erase pulse. Typically, conduction tested single direction through string memory cells determine if string sufficiently erased. For example, conduction single direction tested by determining if bit line NAND string charges predetermined level with all cells biased conduct if erased. In this manner, number cells quickly verified without slowing device performance undesirable level.

For example, erase verify conditions such those illustrated column 380 FIG. 6 applied string memory cells determine if string sufficiently erased after applying erase voltage. An erase voltage reapplied strings or blocks failing verification operation then storage elements are verified again determine if they were successfully erased. Individual memory cells, strings, or blocks determined defective if they fail predetermined number erase verification operations.

Column 380 FIG. 6 illustrates exemplary erase verification bias conditions that used verify that NAND string, such string illustrated FIG. 2, erased after applying erase voltage selected string. Although much disclosure presented with respect four cell NAND string, it understood that principles embodiments described herein used with any number storage elements string. Additionally, actual voltages depicted FIG. 6 may vary by needs characteristics particular implementations.

With reference FIG. 2, read voltage 5V applied select gates 120 122 turn each them on. The voltages applied select gates need not equal so long each applied voltage sufficient turn transistor. The bit line string, e.g bit line 126 , grounded while source, e.g. source line 128 , raised Vdd (e.g., 2.7V). The control gate each memory cells string grounded or supplied with another voltage that sufficient turn erased memory cell. If each cell sufficiently erased threshold voltage below zero volts (or another gate voltage being applied), string conduct bit line should begin charge. If bit line charges above Vsense (e.g., 1.5V) after some predetermined period time (e.g., 9.2 usec), it determined that string sufficiently erased. If bit line does not charge Vsense, erase pulse reapplied verification operation repeated. If predetermined number attempts already been made erase string, string determined defective or otherwise unusable.

Although such verification operation useful for verifying erasure detecting some defective strings or sectors, it unable detect all defects fully verify that string properly erased.

FIG. 7 cross-sectional view NAND string depicted FIGS. 1 2. During erase verify operation, under indicated bias conditions FIG. 6, current flow source side drain side string induced if cells are sufficiently erased, illustrated by arrow 402 . Certain defects transistors such select gate 120 , however, masked such verify operations thus, go undetected.

Select gates, such gate 120 gate 122 , become defective during operation because various breakdowns transistors. For example, select gate transistor may damaged due charges trapped oxide layer between gate channel illustrated FIG. 7 with respect gate 120 . FIG. 7 depicts trapping charge between control gate select gate 120 N+ diffused layer 138 area 406 . Charges become trapped oxide layer after repeated programming erase operations. The trapped charge cause breakdown transistor apparent increase threshold voltage select gate 120 , for example. The increased threshold voltage, seen control gate, cause subsequent read operation improperly read state one or more memory cells string controlled by select gate.

During erase verification operation, each transistor string conductive, causing left side select gate 120 or 122 approximately source side voltage level (e.g., Vdd or 2.7V). This positive voltage source side select gate 120 or 122 may sufficient mask any charges trapped oxide layer. With trapped charge masked by source side voltage, transistor able conduct under applied gate voltage. The larger potential source side string induce current flow through channel indicated by arrow 402 , bit line able charge, string passes erase verification operation.

During subsequent read operation one or more cells string, however, trapped charge may not masked transistor may not function properly. For example, erased memory cell may read being programmed due inability string discharge through defective gate. Column 384 FIG. 6 illustrates exemplary bias conditions that may used read individual cell for erased state. Vcc+Vt (e.g., 4.1V) applied each select gate turn gate on. Vread (5.0V) applied each unselected word line insure that each unselected cell turned on, while word line cell selected for reading grounded or supplied with another voltage sufficient turn erased storage element. After pre-charging bit line 0.7V waiting for period time (e.g., 6.7 usec), bit line charge sensed. If bit line discharges below Vsense (e.g., 0.45V), selected cell determined turned under applied voltage verified erased state. If cell was turned with 0V applied its gate, determined by bit line discharging specified level during select period time, threshold voltage selected cell should below 0V. Thus, cell verified erased.

A trapped charge select gate 120 or 122 , however, may cause bit line not properly discharge under applied bias conditions for read operation. Select gate 120 , for example, may not turn with 4.7V applied its control gate due trapped charge raising threshold voltage select gate. Under read bias conditions, 0V appear left side select gate 120 , while Vdd appear drain side. Under these conditions, there no voltage mask trapped charge select gate, thus, gate may not turn under conditions designed turn properly operating transistor. Consequently, one or more erased memory cells string may improperly read programmed.

In accordance with one embodiment, additional operation performed after, or part of, erase verification operation more comprehensively determine that string erased functioning properly. The additional operation test conduction or current flow through string direction opposite that tested during initial erase verification operation. In this manner, transistors having defects that are masked during erase verification operation detected by testing conduction opposite direction. A NAND string only verified erased if it passes erase verification test also read erased state.

Column 382 FIG. 6 illustrates set bias conditions for reading string for erased state accordance with one embodiment that performed test conduction string. A voltage Vcc+Vt (e.g., 4.1V) applied turn select gates 120 122 . The voltages applied select gates need not equal so long each applied voltage sufficient turn transistor. A verify voltage, which any voltage sufficient turn erased memory cell (e.g., 0V), applied word line for each storage element. By applying 0V word line for each storage element NAND string, each storage element simultaneously read for erased state. Or put another way, entire NAND string read for erased state single operation. The bit line precharged level 0.7V, for example, while source line grounded. With bias conditions so applied, current direction arrow 404 (see FIG. 7) induced channel NAND string if each cell erased select gates are functioning properly. After pre-charing bit line 0.7V waiting period time, voltage bit line sensed. If bit line discharges below Vsense (e.g., 0.45V) after period time (e.g., 6.7 usec), string read being erased state. If however, bit line does not discharge specified time, string read programmed. Even with each memory cell properly erased sufficiently low threshold voltage, bit line may not discharge. For example, if select gate 120 or 122 defective, it may not turn under applied bias conditions. Thus, current flow drain source blocked string not discharge.

In this manner, additional verification determine if string erased performed. By checking for current flow direction opposite that checked during erase verification operation, more comprehensive verification erased condition detection defective cells accomplished. Defects that may been masked during initial erase verification detected provide improved erase verification allow defective portions memory mapped out.

FIG. 8 flowchart method for performing more comprehensive erase verification during user operation accordance with one embodiment. At step 560 , user request erase or program block or other unit memory cells received by controller 318 . This request come any number host devices communication with memory system. Address data designating one or more sectors or divisions thereof input data input/output buffer 312 controller 318 where it recognized latched by state machine 316 . Controller 318 , state machine 316 , various control circuits decode select physical sectors corresponding request. At step 562 , one or more selected memory blocks are erased. In one embodiment, block erased according method illustrated expanded box step 562 . The illustrated steps used erase one or more strings one or more blocks. For example, one embodiment, plurality strings comprising block are simultaneously erased parallel according illustrated steps.

An erase voltage or pulse applied one or more sectors step 502 . Any number means for erasing memory cells used accordance with various embodiments. At step 504 , string storage elements are verified for erased state according column 380 FIG. 6. Conduction through string first direction verified step 504 under conditions turn all erased memory cells string. At step 506 , status erase verification determined. If string was not minimally conductive (e.g, bit line did not sufficiently charge under applied conditions), operation proceeds step 508 where verify count compared with threshold number verify attempts (e.g., 20). If count below threshold value, method continues step 502 where erase pulse or voltage applied selected sector again. If count exceeded threshold value, string and/or block determined not sufficiently erased status fail returned for initial verification step 510 . If it determined step 506 that erase verification was successful, operation proceeds step 514 where read for erased state operation according column 382 FIG. 6 performed string. In one embodiment, reading string for erased state 514 includes testing conduction or current flow through string opposite direction that tested step 504 . In one embodiment, each memory cell string simultaneously read for erased state step 514 (i.e., entire NAND string read for erased state single operation). At step 516 , status read for erased state operation determined. If string was not read erased, status fail for erase operation reported step 510 . If string was read erased, status pass reported step 518 .

After performing erase verification operation read for erased state operation one or more strings block cells, status erase operation determined step 564 . If erase verification operation verifies string erased read for erased state operation reads string erased (as illustrated by step 518 ), erase operation determined been successful status pass returned for erase operation. At step 566 , string or block enabled for programming response successful erase operation. If, however, erase verification operation unable verify string erased, or erase verification operation verifies string erased read for erased state operation reads least one element string programmed (as illustrated by step 510 ), erase operation determined failed. At step 568 , string determined defective. At step 570 , techniques for accommodating defective string performed. For example, defective string may mapped alternate string within block or entire block may mapped out use.

Numerous schemes for handling defective cells, stings, or blocks used accordance with various embodiments. For example, individual memory cell, string, or block mapped alternate cells, strings, or blocks set aside for such use. In embodiments, alternate cells or strings are provided end sectors for use defect mapping. Various defect mapping schemes, including techniques for mapping individual memory cells are more fully described U.S. Pat. No. 6,684,345, entitiled, “Flash EEprom System,” incorporated by reference herein.

FIG. 9 flowchart accordance with one embodiment for performing steps 504 – 506 FIG. 8. After attempting erase group cells step 502 , set erase verify bias conditions are applied string step 530 . In one embodiment, erase verify bias conditions are substantially shown column 380 FIG. 6. These bias conditions are used test for proper current flow or conduction first direction through string under conditions sufficient turn all erased cells string. Step 532 illustrates delay for period time (t) before sensing voltage bit line. The time period vary by embodiment but established time sufficient for bit line charge level indicating that string conductive under applied conditions. After waiting predetermined amount time (t), bit line voltage sensed using any number means for determining voltage thereof step 534 .

At step 536 , sensed bit line voltage compared reference voltage level such Vsense. If bit line charged above threshold level, status pass reported step 538 for erase verification process. If bit line not charged above reference voltage during period time, status fail reported step 540 . From steps 538 540 , operation continues step 514 or step 508 FIG. 8. It appreciated that voltages discussed are exemplary may modified given implementation. For example, values Vsense (t) modified test for different level charge different time. If Vsense increased, period time before sensing bit line voltage increased by corresponding amount. Because bit line takes some period time charge under applied bias conditions, amount time before sensing bit line voltage should selected correspond time which bit line should reach chosen voltage level. In this manner, proper operation string under selected bias conditions verified.

FIG. 10 flowchart accordance with one embodiment for performing steps 514 516 FIG. 8. After successfully verifying erasure string step 506 , set bias conditions read least one storage element string for erased condition applied string. In one embodiment, each storage element simultaneously read (entire NAND string read single operation) for erased state using conditions substantially shown by read for erased state bias conditions illustrated column 382 FIG. 6. A verify voltage that sufficient turn erased storage element (e.g., 0V) applied word line each element string read entire string for erased condition. The bias conditions applied part read for erased state operation test for proper current flow or conduction second direction through string. Step 552 represents delay for period time (t) before sensing bit line voltage. The time period may vary by embodiment, but with erase verification operation, established time sufficient for bit line discharge level indicating that string conductive operating properly under applied conditions. In one embodiment, for example, period time 6.7 usec.

After waiting period time (t), bit line voltage sensed step 554 . At step 556 , sensed bit line voltage compared threshold voltage Vsense (e.g., 0.45V). If bit line discharged below Vsense after period time (t), status erased returned for read for erased state operation step 558 . If bit line not discharged below Vsense after period time, status programmed for read for erased state operation reported step 560 . From steps 558 560 , operation continues steps 518 or 510 .

In accordance with method FIGS. 8–10, more comprehensive erase verification non-volatile memory accomplished. By testing conduction through string memory cells two directions, string more fully verified sufficiently erased. Furthermore, defective elements string whose breakdown may masked during conventional erase verification operations detected. For example, defective select gate whose damaged condition masked during typical erase verification operation detected. A string that passes erase verification operation but that subsequently read having least one programmed cell determined least one defective device string. The string, column string, or block string mapped alternate location memory accommodate detected defect.

In various embodiments, read for erased state operation combined with erase verification operation one or more steps during erase sequence. For example, multi-state techniques for operating non-volatile storage elements, erased memory cells are subjected soft-programming operation prior programming memory cells selected target physical state. When flash memory cells are erased according one embodiment, goal that all erased cells negative threshold voltage with predefined range negative threshold voltages. However, practice, erase process may result some cells having negative threshold voltage below predefined range. Memory cells having threshold voltage that too low may not subsequently program properly. Thus, some devices perform what called soft program. That is, memory cells with threshold voltages having significantly lower values within predefined range receive small amount programming so that threshold voltage raised within predefined range. After soft-programming, memory cells are verified again determine if they are predefined erased range result soft-programming operation.

In such embodiments utilizing soft-programming techniques, for example, one read for erased state operation sufficient adequately test cell. A read for erased state operation may performed only after first successful erase verification operation (i.e., prior soft-programming). The erase verification operation verify conduction first direction through string including cell. The read for erased state verify conduction, thus proper operating conditions string opposite direction. Since proper operation confirmed by single read for erased state operation, there no need perform second read for erased state operation following erase verification operation following soft-programming. In another embodiment, read for erased state operation performed after soft-programming rather than before. In yet other embodiments, read for erased state operation performed both times.

Although much present disclosure been directed erase verification defect detection during user operation memory device, principles techniques also used during manufacturing provide more comprehensive erase verification defect detection. As previously discussed, manufacturing testing processes typically involve reading each bit or memory cell device. A random pattern may programmed array memory cells then each cell read. If state read cell does not match state for which it was programmed it determined defective. Additionally, each cell may read after erasing array. If cell reads programmed after being erased, it determined defective. In one embodiment, testing done during manufacturing by using test pins bypassing controller memory device.

The process reading each cell during test process time-consuming. In accordance with one embodiment, bias conditions shown column 382 FIG. 6 are used read string for erased state during manufacturing process. Reading strings array for erased state replace previous process individually reading each cell array. For example, after erasing cell array during test process, individual strings are read for erased state under bias conditions column 382 (i.e., each cell string simultaneously read for erased state). Those strings that read programmed determined defective. With reading done string basis rather than individual cell basis, time for reading for erased state decreased substantially. In fact, time decrease division time required individually read each cell by number cells string.

In one embodiment, reading strings array for erased state incorporated within erase verification during test process. For example, rather than verify erasure array using bias conditions column 380 exclusively, additional verification step performed under bias conditions column 382 . Individual strings array are only verified erased if they pass erase verification under bias conditions column 380 are read erased state under conditions column 382 . When strings are read for erased state during erase verification, separate read each cell for erased state bypassed because cells already been tested during erase verification.

Much present disclosure been presented under assumption that that verification process performed by applying particular voltage control gate determining whether memory cell turns or off. However, there are other means verifying (and reading) memory cell other verification parameters determine state memory cell that also used within spirit present invention. For example, current-sensing system used which current storage unit under certain read condition compared with set reference currents. In another embodiment, state storage unit determined using number different parameters. For example, determination cell's stored charge level performed by current sensing, where magnitude its conduction, using fixed bias conditions, sensed. Alternatively, such determination made through sensing threshold voltages, where onset such conduction sensed using various steering gate bias conditions. Alternatively, determination performed dynamically by having cell's charge-level determined driver-strength control discharge rate dynamically held sense node (by, e.g. pre-charged capacitor). By sensing time reach given discharge level, stored charge level determined. In this case, parameter indicative cells condition time. This approach described U.S. Pat. No. 6,222,762, incorporated herein by reference its entirety. Another alternative technique one which state storage unit determined using frequency parameter, described U.S. Pat. No. 6,044,019, which hereby incorporated by reference its entirety. Current sensing approaches are more fully developed U.S. Pat. No. 5,172,338, which also incorporated by reference its entirety.

The above examples are provided with respect NAND type flash memory. However, principles present invention application other types non-volatile memories, including those currently existing those contemplated use new technology being developed.

The foregoing description embodiments present invention been provided for purposes illustration description. It not intended exhaustive or limit invention precise forms disclosed. Many modifications variations apparent practitioner skilled art. Embodiments were chosen described order best describe principles invention its practical application, thereby enabling others skilled art understand invention, various embodiments with various modifications that are suited particular use contemplated. It intended that scope invention defined by following claims their equivalents.